Gate-all-around integrated circuit structures having devices with source/drain-to-substrate electrical contact

Patent metadata

Field	Value
Publication number	US-11908856-B2
Application number	US-201916719257-A
Country	US
Kind code	B2
Filing date	Dec 18, 2019
Priority date	Dec 18, 2019
Publication date	Feb 20, 2024
Grant date	Feb 20, 2024

Abstract

Gate-all-around structures having devices with source/drain-to-substrate electrical contact are described. An integrated circuit structure includes a first vertical arrangement of horizontal nanowires above a first fin. A first gate stack is over the first vertical arrangement of horizontal nanowires. A first pair of epitaxial source or drain structures is at first and second ends of the first vertical arrangement of horizontal nanowires. One or both of the first pair of epitaxial source or drain structures is directly electrically coupled to the first fin. A second vertical arrangement of horizontal nanowires is above a second fin. A second gate stack is over the second vertical arrangement of horizontal nanowires. A second pair of epitaxial source or drain structures is at first and second ends of the second vertical arrangement of horizontal nanowires. Both of the second pair of epitaxial source or drain structures is electrically isolated from the second fin.

First claim

What is claimed is:

1. An integrated circuit structure, comprising:
a first vertical arrangement of horizontal nanowires above a first fin;
a first gate stack over the first vertical arrangement of horizontal nanowires;
a first pair of epitaxial source or drain structures at first and second ends of the first vertical arrangement of horizontal nanowires, one or both of the first pair of epitaxial source or drain structures directly electrically coupled to the first fin;
a second vertical arrangement of horizontal nanowires above a second fin;
a second gate stack over the second vertical arrangement of horizontal nanowires; and
a second pair of epitaxial source or drain structures at first and second ends of the second vertical arrangement of horizontal nanowires, both of the second pair of epitaxial source or drain structures electrically isolated from the second fin, wherein the second pair of epitaxial source or drain structures has a bottommost surface vertically between a bottommost nanowire of the second vertical arrangement of horizontal nanowires and an uppermost surface of the second fin.

2. The integrated circuit structure of claim 1 , wherein the first and second pairs of epitaxial source or drain structures are first and second pairs of non-discrete epitaxial source or drain structures.

3. The integrated circuit structure of claim 1 , wherein the first and second fins each comprises a portion of a bulk silicon substrate.

4. The integrated circuit structure of claim 1 , wherein the nanowires of the first and second vertical arrangements of horizontal nanowires comprise silicon.

5. The integrated circuit structure of claim 4 , wherein the first and second pairs of epitaxial source or drain structures comprise silicon germanium.

6. The integrated circuit structure of claim 1 , wherein the nanowires of the first and second vertical arrangements of horizontal nanowires comprise silicon germanium.

7. The integrated circuit structure of claim 1 , wherein each of the first and second gate stacks comprises a high-k gate dielectric layer and a metal gate electrode.

8. The integrated circuit structure of claim 1 , wherein both of the pair of epitaxial source or drain structures are directly electrically coupled to the first fin, the integrated circuit structure further comprising a trench in the first fin, the trench beneath the first gate stack.

9. The integrated circuit structure of claim 1 , wherein both of the pair of epitaxial source or drain structures are directly electrically coupled to the first fin, the integrated circuit structure further comprising a heavily doped region in the first fin, the heavily doped region beneath the first gate stack.

10. An integrated circuit structure, comprising:
a first vertical arrangement of horizontal nanowires above a first fin;
a first gate stack over the first vertical arrangement of horizontal nanowires;
a first pair of epitaxial source or drain structures at first and second ends of the first vertical arrangement of horizontal nanowires, one of the first pair of epitaxial source or drain structures directly electrically coupled to the first fin, and the other of the first pair of epitaxial source or drain structures electrically isolated from the first fin;
a second vertical arrangement of horizontal nanowires above a second fin;
a second gate stack over the second vertical arrangement of horizontal nanowires; and
a second pair of epitaxial source or drain structures at first and second ends of the second vertical arrangement of horizontal nanowires, both of the second pair of epitaxial source or drain structures electrically isolated from the second fin, wherein the second pair of epitaxial source or drain structures has a bottommost surface vertically between a bottommost nanowire of the second vertical arrangement of horizontal nanowires and an uppermost surface of the second fin.

11. The integrated circuit structure of claim 10 , wherein the first and second pairs of epitaxial source or drain structures are first and second pairs of non-discrete epitaxial source or drain structures.

12. The integrated circuit structure of claim 10 , wherein the first and second fins each comprises a portion of a bulk silicon substrate.

13. The integrated circuit structure of claim 10 , wherein the nanowires of the first and second vertical arrangements of horizontal nanowires comprise silicon.

14. The integrated circuit structure of claim 13 , wherein the first and second pairs of epitaxial source or drain structures comprise silicon germanium.

15. The integrated circuit structure of claim 10 , wherein the nanowires of the first and second vertical arrangements of horizontal nanowires comprise silicon germanium.

16. The integrated circuit structure of claim 10 , wherein each of the first and second gate stacks comprises a high-k gate dielectric layer and a metal gate electrode.

17. A computing device, comprising:
a board; and
a component coupled to the board, the component including an integrated circuit structure, comprising:
a first vertical arrangement of horizontal nanowires above a first fin;
a first gate stack over the first vertical arrangement of horizontal nanowires;
a first pair of epitaxial source or drain structures at first and second ends of the first vertical arrangement of horizontal nanowires, one or both of the pair of epitaxial source or drain structures directly electrically coupled to the first fin;
a second vertical arrangement of horizontal nanowires above a second fin;
a second gate stack over the second vertical arrangement of horizontal nanowires; and
a second pair of epitaxial source or drain structures at first and second ends of the second vertical arrangement of horizontal nanowires, both of the pair of epitaxial source or drain structures electrically isolated from the second fin, wherein the second pair of epitaxial source or drain structures has a bottommost surface vertically between a bottommost nanowire of the second vertical arrangement of horizontal nanowires and an uppermost surface of the second fin.

18. The computing device of claim 17 , further comprising:
a memory coupled to the board.

19. The computing device of claim 17 , further comprising:
a communication chip coupled to the board.

20. The computing device of claim 17 , wherein the component is a packaged integrated circuit die.

21. The computing device of claim 17 , wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor.

22. The computing device of claim 17 , wherein the computing device is selected from the group consisting of a mobile phone, a laptop, a desk top computer, a server, and a set-top box.

Assignees

• Intel Corp

Inventors

• Guha Biswajeet
• Hsu William
• Lin Chung-Hsun
• Phoa Kinyip
• Golonzka Oleg
• Ghani Tahir
• Kolluru Kalyan
• Jack Nathan
• THOMSON Nicholas
• Kar Ayan
• Orr Benjamin

Classifications

• H10D30/6757 Primary

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D30/62

  Fin field-effect transistors [FinFET] · CPC title

• H10D30/6735

  having gates fully surrounding the channels, e.g. gate-all-around · CPC title

• H10D62/121

  oriented parallel to substrates · CPC title

• H10D84/0135

  Manufacturing their gate conductors · CPC title