Multi-die memory device with peak current reduction

Patent metadata

Field	Value
Publication number	US-11908812-B2
Application number	US-202117176787-A
Country	US
Kind code	B2
Filing date	Feb 16, 2021
Priority date	Dec 17, 2020
Publication date	Feb 20, 2024
Grant date	Feb 20, 2024

Abstract

A memory device including a substrate including a substrate contact pad. The memory device includes a first memory die including a first power supply contact pad electrically coupled to the substrate contact pad and a first power supply circuit on the first memory die. The first memory die further includes a first electrostatic discharge (ESD) power clamp contact pad electrically coupled to the substrate contact pad and a first ESD power clamp circuit on the first memory die. The memory device further includes a second memory die including a second power supply contact pad electrically coupled to the substrate contact pad and a second power supply circuit on the second memory die and a second ESD power clamp contact pad electrically coupled to a second ESD power clamp circuit on the second memory die, wherein the second ESD power clamp contact pad is electrically disconnected from the substrate contact.

First claim

What is claimed is:

1. A device comprising:
a substrate comprising a first substrate contact, a second substrate contact, and a third substrate contact;
a first memory die coupled to the substrate, the first memory die comprising:
a first power supply contact pad electrically coupled to the first substrate contact and a first power supply circuit on the first memory die;
a first electrostatic discharge (ESD) power clamp contact pad electrically coupled to the first substrate contact and a first ESD power clamp circuit on the first memory die; and
a first data bus contact electrically coupled to the second substrate contact and a first data bus on the first memory die;

a second memory die comprising:
a second power supply contact pad electrically coupled to the first substrate contact and a second power supply circuit on the second memory die;
a second ESD power clamp contact pad electrically coupled to a second ESD power clamp circuit on the second memory die, wherein the second ESD power clamp contact pad is electrically disconnected from the first substrate contact and the second substrate contact; and
a second data bus contact electrically coupled to the second substrate contact and a second data bus on the second memory die; and

a third memory die comprising a third data bus contact electrically coupled to the third substrate contact and a third data bus on the third memory die.

2. The device of claim 1 , wherein the first memory die and the second memory die comprise a same physical arrangement.

3. The device of claim 1 , wherein the first memory die and the second memory die are arranged in a stack coupled to the substrate.

4. The device of claim 1 , wherein the first ESD power clamp circuit comprises one or more passive circuit elements and one or more active circuit elements to provide ESD protection to the first memory die and the second memory die.

5. The device of claim 1 , wherein the second ESD power clamp circuit does not contribute to a peak current level of the device during a power on operation of the device.

6. The device of claim 1 , wherein the first substrate contact is electrically coupled to the first power supply contact pad and the first ESD power clamp contact pad by a single wirebond and a single solder ball.

7. The device of claim 1 , wherein the first substrate contact is electrically coupled to the second power supply contact pad by a wirebond between the first power supply contact pad and the second power supply contact pad.

8. The device of claim 1 , wherein the second ESD power clamp circuit does not contribute to an overall current consumption level of the device.

9. The device of claim 1 , wherein the first power supply contact pad corresponds to a positive voltage supply of the first memory die.

10. The device of claim 1 , wherein the first power supply contact pad corresponds to a ground voltage supply of the first memory die.

11. The device of claim 1 , wherein the first memory die comprises a third power supply contact pad.

12. The device of claim 11 , wherein the first power supply contact pad corresponds to a positive voltage supply of the first memory die and the third power supply contact pad corresponds to a ground voltage supply of the first memory die.

13. A system comprising:
a controller; and
a memory device coupled to the controller, the memory device comprising:
a substrate comprising a first substrate contact a second substrate contact, and a third substrate contact;
a first memory die coupled to the substrate, the first memory die comprising:
a first power supply contact pad electrically coupled to the first substrate contact and a first power supply circuit on the first memory die;
a first electrostatic discharge (ESD) power clamp contact pad electrically coupled to the first substrate contact and a first ESD power clamp circuit on the first memory die; and
a first data bus contact electrically coupled to the second substrate contact and a first data bus on the first memory die;

a second memory die comprising:
a second power supply contact pad electrically coupled to the first substrate contact and a second power supply circuit on the second memory die;
a second ESD power clamp contact pad electrically coupled to a second ESD power clamp circuit on the second memory die, wherein the second ESD power clamp contact pad is electrically disconnected from the second substrate contact; and
a second data bus contact electrically coupled to the second substrate contact and a second data bus on the second memory die; and

a third memory die comprising a third data bus contact electrically coupled to the third substrate contact and a third data bus on the third memory die.

14. The system of claim 13 , wherein the first memory die and the second memory die comprise a same physical arrangement.

15. The system of claim 13 , wherein the first memory die and the second memory die are arranged in a stack coupled to the substrate.

16. The system of claim 13 , wherein the first ESD power clamp circuit comprises one or more passive circuit elements and one or more active circuit elements to provide ESD protection to the first memory die and the second memory die; and wherein the second ESD power clamp circuit does not contribute to a peak current level of the memory device during a power on operation of the memory device.

17. The system of claim 13 , wherein the first power supply contact pad corresponds to a positive voltage supply of the first memory die.

18. The system of claim 13 , wherein the first power supply contact pad corresponds to a ground voltage supply of the first memory die.

19. The system of claim 13 , wherein the first memory die comprises a third power supply contact pad; and wherein the first power supply contact pad corresponds to a positive voltage supply of the first memory die and the third power supply contact pad corresponds to a ground voltage supply of the first memory die.

20. A semiconductor device comprising:
a substrate comprising a first substrate contact a second substrate contact and a third substrate contact;
a first memory die coupled to the substrate, the first memory die comprising:
a first power supply contact pad electrically coupled to the first substrate contact and a first power supply circuit on the first memory die;
a first electrostatic discharge (ESD) power clamp contact pad electrically coupled to the first substrate contact and a first ESD power clamp circuit on the first memory die; and
a first data bus contact electrically coupled to the second substrate contact and a first data bus on the first memory die;

a second memory die comprising:
a second power supply contact pad electrically coupled to the first substrate contact and a second power supply circuit on the second memory die;
a second ESD power clamp contact pad electrically coupled to a second ESD power clamp circuit on the second memory die, wherein the second ESD power clamp contact pad is electrically disconnected from the second substrate contact; and
a second data bus contact electrically coupled to the second substrate contact and a second data bus on the second memory die; and

a third memory die comprising a third data bus contact electrically coupled to the third substrate contact and a third data bus on the third memory die.

Assignees

• Micron Technology Inc

Inventors

• Shimizu Yui
• Davis James E

Classifications

• H10W90/752

  between stacked chips · CPC title

• H10W90/24

  at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W72/01

  Manufacture or treatment · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title