Semiconductor devices with post-probe configurability

Patent metadata

Field	Value
Publication number	US-10403585-B2
Application number	US-201816138003-A
Country	US
Kind code	B2
Filing date	Sep 21, 2018
Priority date	Nov 13, 2017
Publication date	Sep 3, 2019
Grant date	Sep 3, 2019

Abstract

A semiconductor device assembly includes a substrate and a die coupled to the substrate. The die includes a first contact pad electrically coupled to a first circuit on the die including at least one active circuit element, a second contact pad electrically coupled to a second circuit on the die including only passive circuit elements, and a plated pad electrically coupling at least a part of the first contact pad to at least a part of the second contact pad. The substrate includes a substrate contact electrically coupled to the plated pad on the die.

First claim

We claim:

1. A semiconductor device assembly, comprising:
a substrate;
a die coupled to the substrate, the die including:
a first contact pad electrically coupled to a first circuit on the die including at least one active circuit element,
a second contact pad electrically coupled to a second circuit on the die including only passive circuit elements, and
a plated pad electrically coupling at least a part of the first contact pad to at least a part of the second contact pad;

wherein the substrate includes a substrate contact electrically coupled to the plated pad on the die,
wherein the die is a first die, the semiconductor device assembly further comprising:
a second die including:
a third contact pad electrically coupled to a third circuit on the second die including at least a second active circuit element, and
a fourth contact pad electrically coupled to a fourth circuit on the second die including only passive circuit elements;

wherein the substrate contact is electrically coupled to the third contact pad on the second die, and
wherein the second die further includes another plated pad electrically coupling at least a part of the third contact pad to at least a part of the fourth contact pad.

2. The semiconductor device assembly of claim 1 , wherein the fourth contact pad on the second die is electrically disconnected from the substrate contact.

3. The semiconductor device assembly of claim 1 , wherein the first and second dies are identical dies, wherein the first contact pad on the first die corresponds to the third contact pad on the second die, and the second contact pad on the first die corresponds to the fourth contact pad on the second die.

4. The semiconductor device assembly of claim 1 , wherein the first and second dies are stacked in a shingled configuration.

5. The semiconductor device assembly of claim 1 , wherein the first circuit is a driver circuit.

6. The semiconductor device assembly of claim 1 , wherein the second circuit includes one or more capacitors to provide electrostatic discharge (ESD) protection.

7. The semiconductor device assembly of claim 1 , wherein the substrate contact is electrically coupled to the plated pad by a wirebond.

8. The semiconductor device assembly of claim 1 , wherein the die is a NAND memory die.

9. A method of making a semiconductor device, comprising:
providing a wafer including a plurality of semiconductor dies, wherein each of the plurality of semiconductor dies includes:
a first contact pad electrically coupled to a first circuit on the semiconductor die including at least one active circuit element, and
a second contact pad electrically coupled to a second circuit on the semiconductor die including only passive circuit elements;

for each of the plurality of semiconductor dies, plating a plated pad electrically coupling at least a part of the first contact pad to at least a part of the second contact pad;
singulating the plurality of semiconductor dies from the wafer, and
before plating the plated pad, probing the first circuit of at least one of the plurality of un-singulated semiconductor dies to determine a packaging density for the plurality of semiconductor dies.

10. The method of claim 9 , wherein the plating the plated pad is based at least in part on the determined packaging density.

11. The method of claim 9 , further comprising:
thinning the wafer based at least in part on the determined packaging density.

Assignees

• Micron Technology Inc

Inventors

• Davis James E
• Duesman Kevin G
• Wright Jeffrey P
• Boyer Warren L

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/752

  between stacked chips · CPC title

• H10W90/24

  at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/5445

  being orthogonal to a side surface of the chip, e.g. parallel arrangements · CPC title