Gate driving circuit and display device having the same

Patent metadata

Field	Value
Publication number	US-11908417-B2
Application number	US-202217728584-A
Country	US
Kind code	B2
Filing date	Apr 25, 2022
Priority date	Jul 14, 2016
Publication date	Feb 20, 2024
Grant date	Feb 20, 2024

Abstract

A gate driving circuit including a controller for providing a first carry signal to a control node, a first pull-up portion for outputting a first clock signal as a first gate signal in accordance with a signal provided to the control node, and a second pull-up portion for outputting a second clock signal with a phase that is different from the first clock signal as a second gate signal in accordance with the signal provided to the control node.

First claim

What is claimed is:

1. A display device comprising:
a display panel comprising a plurality of pixels connected to a first gate line, a second gate line, and a third gate line that are adjacent to one another;
a first gate driving circuit on a first side of the plurality of pixels and comprising a first stage for outputting first and second gate signals having phases that are different from each other; and
a second gate driving circuit on a second side of the plurality of pixels that is opposite the first side of the plurality of pixels, and comprising a second stage for outputting third and fourth gate signals having phases that are different from each other,
wherein the first stage is configured to provide the first gate signal to a first side of the second gate line,
wherein the second stage is configured to provide the fourth gate signal to a second side of the second gate line,
wherein the first stage is configured to provide the second gate signal to a first side of the third gate line,
wherein the second stage is configured to provide the third gate signal to a second side of the first gate line, and
wherein the first stage comprises:
a first pull-up portion for outputting a first clock signal as the first gate signal in accordance with a signal provided to a control node; and
a second pull-up portion for outputting a second clock signal having a phase that is different from a phase of the first clock signal as the second gate signal in accordance with the signal provided to the control node.

2. The display device of claim 1 , wherein the first stage further comprises:
a controller for providing a first carry signal to the control node.

3. The display device of claim 2 , wherein the first pull-up portion comprises a first pull-up transistor comprising:
a gate electrode connected to the control node;
an input terminal for receiving the first clock signal; and
an output terminal for outputting the first gate signal,
wherein the second pull-up portion comprises a second pull-up transistor comprising:
a gate electrode connected to the control node;
an input terminal for receiving the second clock signal; and
an output terminal for outputting the second gate signal, and

wherein the controller comprises:
a gate electrode for receiving the first carry signal;
a first control transistor connected to the control node; and
a control capacitor comprising a first electrode connected to the gate electrode of the first pull-up transistor, and a second electrode connected to the output terminal of the first pull-up transistor.

4. The display device of claim 1 , wherein the second stage comprises:
a controller for providing a first carry signal to a control node;
a first pull-up portion for outputting a first clock signal as the third gate signal in accordance with the first carry signal provided to the control node; and
a second pull-up portion for outputting a second clock signal having a phase that is different from the phase of the first clock signal as the fourth gate signal in accordance with the first carry signal provided to the control node.

5. The display device of claim 4 , wherein the first pull-up portion comprises a first pull-up transistor comprising:
a gate electrode connected to the control node;
an input terminal for receiving the first clock signal; and
an output terminal for outputting the third gate signal,
wherein the second pull-up portion comprises a second pull-up transistor comprising:
a gate electrode connected to the control node;
an input terminal for receiving the second clock signal; and
an output terminal for outputting the fourth gate signal, and

wherein the controller comprises:
a gate electrode for receiving the first carry signal;
a control transistor connected to the control node; and
a control capacitor comprising a first electrode connected to the gate electrode of the first pull-up transistor, and a second electrode connected to the output terminal of the first pull-up transistor.

6. The display device of claim 1 , wherein the first gate driving circuit further comprises a third stage that is adjacent to the first stage, and has a first output terminal and a second output terminal for outputting two respective gate signals having phases that are different from each other,
wherein the second gate driving circuit further comprises a fourth stage that is adjacent to the second stage, and has a first output terminal and a second output terminal for outputting two respective gate signals having phases that are different from each other,
wherein the second output terminal of the third stage is connected to a first side of the first gate line, and
wherein the first output terminal of the fourth stage is connected to a second side of the third gate line.

Assignees

• Samsung Display Co Ltd

Inventors

• Kim Kang Nam
• Hyun You Mee
• Kim Beom Jun
• Lee Jong Hwan
• Lim Sung Hoon
• Cho Duc Han

Classifications

• G09G3/3266 Primary

  Details of drivers for scan electrodes · CPC title

• G09G3/20 Primary

  for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} · CPC title

• G09G3/3677 Primary

  suitable for active matrices only · CPC title

• G11C19/28

  using semiconductor elements (G11C19/14, G11C19/36 take precedence) · CPC title

• G09G2300/0426

  Layout of electrodes and connections · CPC title