Driving circuit and driving method

Patent metadata

Field	Value
Publication number	US-2017193957-A1
Application number	US-201615088137-A
Country	US
Kind code	A1
Filing date	Apr 1, 2016
Priority date	Jan 4, 2016
Publication date	Jul 6, 2017
Grant date	—

Abstract

A driving circuit in this disclosure includes plural stages of shift register circuits. Every stage in the shift register circuits includes an enabling control circuit, a first output circuit, a second output circuit and a disabling control circuit. The enabling circuit is configured to control the voltage of the first operation node according to enabling signal. The first output unit is configured to generate the first driving signal according to the voltage of the first operation node and the first clock signal. The second output unit is configured to generate the second driving signal according to the voltage of the first operation node and the second clock signal. The disabling control unit is used to pull low the voltage of the first operation node and output terminal of the first and second output unit to the reference voltage according to the first, third, and fourth clock signals.

First claim

What is claimed is:

1 . A driving circuit, comprising:
plural stages of shift register circuits configured for generating a plurality of driving signals sequentially, each stage of the shift register circuits comprising:
an enabling control unit configured to control a voltage level of a first operation node according to an enabling signal;
a first output unit electrically coupled to the first operation node, the first output unit being configured to generate a first driving signal at an output terminal of the first output unit according to the voltage level of the first operation node and a first clock signal;
a second output unit electrically coupled to the first operation node, the second output unit being configured to generate a second driving signal at an output terminal of the second output unit according to the voltage level of the first operation node and a second clock signal; and
a disabling control unit electrically coupled to the first output unit and the second output unit, the disabling control unit being configured to pull low the voltage levels of the first operation node, the output terminal of the first output unit and the output terminal of the second output unit to a reference voltage level according to the first clock signal, a third clock signal and a fourth clock signal,
wherein the first clock signal and the third clock signal are complementary to each other, and the second clock signal and the fourth clock signal are complementary to each other.

2 . The driving circuit of claim 1 , wherein the second driving signal in each stage of the shift register circuits is the enabling signal in the next stage of the shift register circuits.

3 . The driving circuit of claim 1 , wherein the enabling control unit is configured to control the voltage level of the first operation node further according to a reset signal.

4 . The driving circuit of claim 3 , wherein the second driving signal in each stage of the shift register circuits is the reset signal in the previous stage of the shift register circuits.

5 . The driving circuit of claim 4 , wherein the enabling control unit comprises:
a first transistor, wherein a control terminal of the first transistor is configured to receive the enabling signal, a first terminal of the first transistor is electrically coupled to the first operation node, and a second terminal of the first transistor is configured to receive a first operation voltage; and a second transistor, wherein a control terminal of the second transistor is configured to receive the reset signal, a first terminal of the second transistor is electrically coupled to the first operation node, and a second terminal of the second transistor is configured to receive a second operation voltage.

6 . The driving circuit of claim 1 , wherein the first output unit further comprises a third transistor, a control terminal of the third transistor is electrically coupled to the first operation node, a first terminal of the third transistor is electrically coupled to the disabling control unit, and a second terminal of the third transistor is configured to receive the first clock signal, and
the second output unit further comprises a fourth transistor, a control terminal of the fourth transistor is electrically coupled to the first operation node, a first terminal of the fourth transistor is electrically coupled to the disabling control unit, and a second terminal of the fourth transistor is configured to receive a second clock signal.

7 . The driving circuit of claim 6 , wherein the first output unit further comprises a first capacitor in the first output unit, a first terminal of the first capacitor is electrically coupled to the control terminal of the third transistor, and a second terminal of the first capacitor is electrically coupled to the first terminal of the third transistor, and
the second output unit further comprises a second capacitor, a first terminal of the second capacitor is electrically coupled to the control terminal of the fourth transistor, and a second terminal of the second capacitor is electrically coupled to the first terminal of the fourth transistor.

8 . The driving circuit of claim 1 , the disabling control unit further comprises:
a first disabling circuit, comprising:
a fifth transistor, wherein a control terminal of the fifth transistor is electrically coupled to a second operation node, a first terminal of the fifth transistor is configured to receive the reference voltage level, and a second terminal of the fifth transistor is electrically coupled to the output terminal of the first output unit; and
a sixth transistor, wherein a control terminal of the sixth transistor is configured to receive a third clock signal, a first terminal of the sixth transistor is configured to receive the reference voltage level, and a second terminal of the sixth transistor is electrically coupled to the output terminal of the first output unit;
a second disabling circuit, comprising:
a seventh transistor, wherein a control terminal of the seventh transistor is electrically coupled to the second operation node, a first terminal of the seventh transistor is configured to receive the reference voltage level, and a second terminal of the seventh transistor is electrically coupled to the output terminal of the second output unit; and
an eighth transistor, wherein a control terminal of the eighth transistor is electrically coupled to the first operation node, a first terminal of the eighth transistor is configured to receive the reference voltage level, and a second terminal of the eighth transistor is electrically coupled to the output terminal of the second output unit; and
a third disabling circuit, comprising:
a ninth transistor, wherein a control terminal of the ninth transistor is electrically coupled to the first operation node, a first terminal of the ninth transistor is configured to receive the reference voltage level, and a second terminal of the ninth transistor is electrically coupled to the second operation node;
a tenth transistor, wherein a control terminal of the tenth transistor is electrically coupled to the second operation node, a first terminal of the tenth transistor is configured to receive the reference voltage level, and a second terminal of the tenth transistor is electrically coupled to the first operation node; and
a third capacitor, wherein a first terminal of the third capacitor is electrically coupled to the second operation node, and a second terminal of the third capacitor is configured to receive the first clock signal.

9 . A driving method, suitable for driving the plural stages of the shift register circuits in the driving circuit of claim 1 , the driving method comprising:
in a first time interval, driving the enabling control unit by the enabling signal for configuring the first operation node to a first enabling level; in a second time interval after the first time interval, enabling the first clock signal for triggering the first output unit to generate a first driving signal at the output terminal of the first output unit, and configuring the first operation node to a second enabling level; in a third time interval after the second time interval, enabling the second clock signal for triggering the second output unit to generate a second driving signal at the output terminal of the second output unit, and configuring the first operation node to a third enabling level; in a fourth time interval after the third time interval, disabling the third clock signal for configuring the first operation node to the second enabling level; and after the fourth time interval, pulling low the voltage level of the first operation node to the reference volta

Assignees

• Chunghwa Picture Tubes Ltd

Inventors

• Liu Han-Lung
• Sung Wei-Lien
• Wang Wen-Chuan
• Chang Shao-Lun
• Lin Shih-Chieh

Classifications

• G11C19/28 Primary

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• G09G2300/0809

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• G09G2310/08

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• G09G3/3688

  suitable for active matrices only · CPC title

• G09G2300/0426

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