Baseboard management controller (BMC) test system and method

Patent metadata

Field	Value
Publication number	US-11907384-B2
Application number	US-202117337686-A
Country	US
Kind code	B2
Filing date	Jun 3, 2021
Priority date	Jun 3, 2021
Publication date	Feb 20, 2024
Grant date	Feb 20, 2024

Abstract

An Information Handling System (IHS) includes multiple hardware devices, and a baseboard Management Controller (BMC) in communication with the plurality of hardware devices. The BMC includes a first processor configured to execute a custom BMC firmware stack, and a second processor including executable instructions for receiving a request to perform a test on the first processor in which the request is received through a secure communication session established with a remote IHS. The instructions further perform the acts of controlling the first processor to perform the test according to the request, the first processor generating test results associated with the test, and transmitting the test results to the remote IHS through the secure communication session.

First claim

The invention claimed is:

1. An Information Handling System (IHS), comprising:
a plurality of hardware devices; and
a baseboard management controller (BMC) in communication with the plurality of hardware devices, the BMC comprising:
a first processor configured to execute a custom BMC firmware stack; and
a second processor in communication with a plurality of test access ports (TAPs) of the first processor, the second processor configured to execute instructions stored in a memory unit to:
receive a request to perform a test on the first processor, the request received through a secure communication session established with a remote IHS;
control the first processor to perform the test according to the request, the first processor to generate test results associated with the test;
transmit the test results to the remote IHS through the secure communication session.

2. The IHS of claim 1 , wherein the instructions are further executed to:
determine whether or not the secure communication session has sufficient rights for to perform the test on the first processor;
disallow the test when the secure communication session does not have the sufficient rights,
wherein the secure communication session is associated with an account for which the rights have been established, and
wherein the rights indicate at least one of a plurality of test types that are allowed to be performed via the secure communication session.

3. The IHS of claim 2 , wherein the account is configured to be modified, via an administrator of the account, to change which test types are allowed via the secure communication session.

4. The IHS of claim 2 , wherein the test types comprise at least one of a boundary scan test, a processor single step test, a stop at breakpoint test, a register or memory access procedure, and a memory dump procedure.

5. The IHS of claim 1 , wherein the first processor comprises an advanced RISC machine (ARM) processor, and the second processor comprises a coprocessor configured to assist the ARM processor to perform one or more functions associated with the operation of the BMC.

6. The IHS of claim 1 , wherein the instructions are further executed to restrict the custom BMC firmware stack from being able to access a portion of the memory units that store the instructions.

7. The IHS of claim 1 , wherein the instructions are further executed to perform the test to:
generate input test data that is inputted into at least a portion of the TAPs of the first processor;
receive output test data that is generated by the first processor on at least a second portion of the TAPs, the output test data comprising the test results.

8. The IHS of claim 1 , wherein the TAPs comprise test pins corresponding to a JTAG specification, the test pins comprising a test data in (TDI) test pin, a test data out (TDO) test pin, a test clock (TCK) test pin, a test mode select (TMS) test pin, and a test reset (TRST) test pin.

9. The IHS of claim 1 , wherein the instructions are further executed to perform the test by:
when the first processor experiences a crash, save at least a portion of the working memory of the custom BMC firmware stack; and
transmit the portion of working memory to the remote IHS via the secure communication session.

10. The IHS of claim 1 , wherein the instructions are further executed to communicate with a third processor to:
receive another request to perform another test on the third processor, the other request received through another secure communication session established with another remote IHS;
control the third processor to perform the other test according to the other request, the third processor to generate test results associated with the other test;
transmit the other test results to the other remote IHS through the other secure communication session.

11. The IHS of claim 1 , wherein the third processor comprises at least one of a complex programmable logic device (CPLD) configured on the IHS, or a PERC processor.

12. A method comprising:
receiving, using instructions stored in at least one memory and executed by at least one processor, a request to perform a test on a first processor, the request received through a secure communication session established with a remote IHS, the first and second process configured on a baseboard management controller (BMC) in communication with the plurality of hardware devices of an information handling system (IHS), the second processor in communication with a plurality of test access ports (TAPs) of the first processor;
controlling, using the instructions, the first processor to perform the test according to the request, the first processor generating test results associated with the test;
transmitting, using the instructions, the test results to the remote IHS through the secure communication session.

13. The method of claim 12 , further comprising:
determining whether or not the secure communication session has sufficient rights for performing the test on the first processor;
disallowing the test when the secure communication session does not have the sufficient rights,
wherein the secure communication session is associated with an account for which the rights have been established, and
wherein the rights indicate at least one of a plurality of test types that are allowed to be performed via the secure communication session.

14. The method of claim 13 , further comprising modifying the account to change which test types are allowed via the secure communication session.

15. The method of claim 12 , further comprising restricting the custom BMC firmware stack from accessing a portion of the memory units that store the instructions.

16. The method of claim 12 , further comprising performing the test by:
generating input test data that is inputted into at least a portion of the TAPs of the first processor; and
receiving output test data that is generated by the first processor on at least a second portion of the TAPs, the output test data comprising the test results.

17. The method of claim 12 , further comprising performing the test by:
when the first processor experiences a crash, save at least a portion of the working memory of the custom BMC firmware stack; and
transmit the portion of working memory to the remote IHS via the secure communication session.

18. The method of claim 12 , further comprising communicating with a third processor to:
receive another request to perform another test on the third processor, the other request received through another secure communication session established with another remote IHS;
control the third processor to perform the other test according to the other request, the third processor generating test results associated with the other test;
transmit the other test results to the other remote IHS through the other secure communication session.

19. A baseboard management controller (BMC) in communication with a plurality of hardware devices of an information handling system (IHS), the BMC comprising:
a first processor configured to execute a custom BMC firmware stack; and
a second processor in communication with a plurality of test access ports (TAPs) of the first processor, the second processor configured to execute instructions stored in a memory unit to:
receive a request to perform a test on the first processor, the request received through a secure communication session established with a remote IHS;
control the first processor to perform the test according to the request, the first processor to generate te

Assignees

• Dell Products Lp

Inventors

• Lambert Timothy M
• Cho Eugene David

Classifications

• G06F21/62 Primary

  Protecting access to data via a platform, e.g. using keys or access control rules · CPC title

• G06F11/273

  Tester hardware, i.e. output processing circuits {(G06F11/263 takes precedence)} · CPC title

• G06F11/2733

  Test interface between tester and unit under test · CPC title

• G06F11/2736

  using a dedicated service processor for test · CPC title

• G06F21/629 Primary

  to features or functions of an application · CPC title