Testing circuit board with self-detection function and self-detection method thereof

Patent metadata

Field	Value
Publication number	US-10184976-B2
Application number	US-201715622964-A
Country	US
Kind code	B2
Filing date	Jun 14, 2017
Priority date	Dec 12, 2016
Publication date	Jan 22, 2019
Grant date	Jan 22, 2019

Abstract

The present disclosure illustrates a testing circuit board with self-detection function and a self-detection method. A test for a to-be-tested circuit board is executed and a self-detection for a testing circuit board is performed by a JTAG chip. After the self-detection is passed, a first JTAG connection interface and a second JTAG connection interface are conducted by a controller, a multiplexer and a switch chip, to connect test circuit boards in series. Therefore, the efficiency of solving self-detection of JTAG chip with series connection conveniently and quickly may be achieved.

First claim

What is claimed is:

1. A testing circuit board with self-detection function, comprising:
a first joint test action group (JTAG) connection interface configured to be electrically coupled to a JTAG controller or other testing circuit board, and comprising a first test clock (TCK) pin, a first test mode selection (TMS) pin, a first test data input (TDI) pin and a first test data output (TDO) pin;
a JTAG chip electrically coupled to the first TCK pin, the first TMS pin and the first TDI pin, wherein a JTAG controller controls the JTAG chip to perform self-detection of the testing circuit board, and when the testing circuit board passes the self-detection, the JTAG chip generates a communication signal;
a controller electrically coupled to the JTAG chip;
a multiplexer electrically coupled to a data output pin of the JTAG chip and the controller, wherein in default setting, the first TDO pin is electrically coupled to the data output pin of the JTAG chip through the multiplexer;
a switch chip electrically coupled to the first TDO pin, the controller and the multiplexer;
a buffer electrically coupled to the first TCK pin and the first TMS pin; and
a second JTAG connection interface configured to be electrically coupled to the first JTAG connection interface of other testing circuit board, and comprising a second TCK pin, a second TMS pin, a second TDI pin and a second TDO pin, wherein the second TCK pin and the second TMS pin are electrically coupled to the buffer, the second TDI pin is electrically coupled to the multiplexer, and the second TDO pin is electrically coupled to the switch chip; and
a test connection interface electrically coupled to the JTAG chip and a to-be-tested circuit board separately, wherein the JTAG chip detects the to-be-tested circuit board through the test connection interface;
wherein, after the JTAG chip generates the communication signal, the controller receives the communication signal from the JTAG chip to generate a selection (SEL) signal, and the multiplexer breaks electrical connection between the first TDO pin and the data output pin of the JTAG chip, and conducts the second TDI pin with the data output pin of the JTAG chip according to the SEL signal, and the switch chip conducts the first TDO pin with the second TDO pin according to the SEL signal, so that the first JTAG connection interface is conducted with the second JTAG connection interface, the testing circuit board and the other testing circuit board are connected in series through the first JTAG connection interface and the second JTAG connection interface.

2. The testing circuit board according to claim 1 , wherein the JTAG controller controls the JTAG chip, by boundary scan technology, to detect the to-be-tested circuit board or perform the self-detection of the testing circuit board.

3. The testing circuit board according to claim 2 , the JTAG controller scans an ID code of the JTAG chip to detect stability of a JTAG boundary scan chain.

4. The testing circuit board according to claim 3 , wherein the JTAG controller resets a boundary scan chain of the JTAG chip, and reads the ID code of the JTAG chip and determines whether the ID code is consistent, and pushes a boundary scan sample and a huge amount of data, by the boundary scan technology, to determine whether an output result is consistent, thereby performing the self-detection of the testing circuit board.

5. The testing circuit board according to claim 1 , wherein the buffer is configured to improve signal strength and anti-interference of the signals transmitted from the first TCK pin, the first TMS pin, the second TCK pin and the second TMS pin, thereby preventing from interference caused by signal reflection from other testing circuit board.

6. A self-detection method for a testing circuit board with self-detection function, comprising:
providing a testing circuit board which comprise a first joint test action group (JTAG) connection interface, a JTAG chip, a controller, a multiplexer, a switch chip, a buffer, a second JTAG connection interface and a test connection interface;
in the first JTAG connection interface, providing a first test clock (TCK) pin, a first test mode selection (TMS) pin, a first test data input (TDI) pin and a first test data output (TDO) pin;
in the second JTAG connection interface, providing a second TCK pin, a second TMS pin, a second TDI pin and a second TDO pin;
electrically coupling the first JTAG connection interface to a JTAG controller or a second JTAG connection interface of other testing circuit board;
electrically coupling the JTAG chip to the first TCK pin, the first TMS pin and the first TDI pin;
electrically coupling the controller to the JTAG chip;
electrically coupling the multiplexer to the controller and a data output pin of the JTAG chip, wherein in default setting, the first TDO pin is electrically coupled to the data output pin of the JTAG chip through the multiplexer;
electrically coupling the switch chip to the first TDO pin, the controller and the multiplexer;
electrically coupling the buffer to the first TCK pin and the first TMS pin;
electrically coupling the second TCK pin and the second TMS pin to the buffer, electrically coupling the second TDI pin to the multiplexer, and electrically coupling the second TDO pin to the switch chip;
electrically coupling the test connection interface to the JTAG chip and a to-be-tested circuit board separately;
controlling, by the JTAG controller, the JTAG chip to detect the to-be-tested circuit board through the test connection interface;
controlling, by the JTAG controller, the JTAG chip to perform self-detection of the testing circuit board;
generating a communication signal by the JTAG chip when the testing circuit board passes the self-detection;
in the controller, receiving the communication signal from the JTAG chip to generate a selection (SEL) signal; and
breaking, by the multiplexer, electrical connection between the first TDO pin and the data output pin of the JTAG chip according to the SEL signal, and conducting, by the multiplexer, the second TDI pin with the data output pin of the JTAG chip, and conducting, by the switch chip, the first TDO pin with the second TDO pin according to the SEL signal, thereby conducting the first JTAG connection interface with the second JTAG connection interface, and connecting the testing circuit board and the other testing circuit board in series through the first JTAG connection interface and the second JTAG connection interface.

7. The self-detection method according to claim 6 , wherein the JTAG controller controls the JTAG chip, by boundary scan technology, to detect the to-be-tested circuit board or perform the self-detection of the testing circuit board.

8. The self-detection method according to claim 7 , wherein the JTAG controller scans an ID code of the JTAG chip to detect stability of a JTAG boundary scan chain.

9. The self-detection method according to claim 8 , wherein the JTAG controller resets a boundary scan chain of the JTAG chip, and reads the ID code of the JTAG chip and determines whether the ID code is consistent, and pushes a boundary scan sample and a huge amount of data, by the boundary scan technology, to determine whether an output result is consistent, thereby performing the self-detection of the testing circuit board.

10. The self-detection method according to claim 6 , wherein the buffer is configured to improve signal strength and anti-interference of the signals transmitted from the first TCK pin, the first TMS pin, the second TCK pin and the second TMS pin, thereby preventing from interference caused by signal reflection from other testing circuit board.

Assignees

• Inventec Pudong Tech Corp
• Inventec Corp

Inventors

• Song Ping

Classifications

• G01R31/3177

  Testing of logic operation, e.g. by logic analysers · CPC title

• G01R31/2884 Primary

  using dedicated test connectors, test elements or test circuits on the IC under test (G01R31/2855 takes precedence) · CPC title

• G01R31/31723

  Hardware for routing the test signal within the device under test to the circuits to be tested, e.g. multiplexer for multiple core testing, accessing internal nodes (routing the test signal to or from the device under test G01R31/31926) · CPC title

• G01R31/318572

  Input/Output interfaces · CPC title

• G01R31/31701

  Arrangements for setting the Unit Under Test [UUT] in a test mode · CPC title