Digital-to-analog converter, data processing system, base station, and mobile device

Patent metadata

Field	Value
Publication number	US-11901908-B2
Application number	US-201917754148-A
Country	US
Kind code	B2
Filing date	Dec 23, 2019
Priority date	Dec 23, 2019
Publication date	Feb 13, 2024
Grant date	Feb 13, 2024

Abstract

A Digital-to-Analog Converter, DAC, is provided. The DAC comprises one or more first DAC cells configured to generate a first analog signal based on first digital data. The one or more first DAC cells are coupled to a first output node for coupling to a first load. The DAC comprises one or more second DAC cells configured to generate a second analog signal based on second digital data. The one or more second DAC cells are coupled to a second output node for coupling to a second load. The one or more first DAC cells and the one or more second DAC cells are couplable to a power supply for drawing a supply current. The DAC further comprises a data generation circuit configured to generate the second digital data based on the first digital data.

First claim

What is claimed is:

1. A digital-to-analog converter, comprising:
one or more first digital-to-analog converter cells configured to generate a first analog signal based on first digital data, wherein the one or more first digital-to-analog converter cells are coupled to a first output node for coupling to a first load;
one or more second digital-to-analog converter cells configured to generate a second analog signal based on second digital data, wherein the one or more second digital-to-analog converter cells are coupled to a second output node for coupling to a second load, and wherein the one or more first digital-to-analog converter cells and the one or more second digital-to-analog converter cells are couplable to a power supply for drawing a supply current; and
a data generation circuit configured to generate the second digital data based on the first digital data.

2. The digital-to-analog converter of claim 1 , wherein the one or more first digital-to-analog converter cells and the one or more second digital-to-analog converter cells are capacitive digital-to-analog converter cells.

3. The digital-to-analog converter of claim 1 , wherein the one or more first digital-to-analog converter cells and the one or more second digital-to-analog converter cells are resistive digital-to-analog converter cells.

4. The digital-to-analog converter of claim 1 , wherein the data generation circuit is configured to generate the second digital data such that the second digital data is the opposite of the first digital data.

5. The digital-to-analog converter of claim 1 , wherein the data generation circuit is configured to generate the second digital data such that a signal value represented by the second digital data corresponds to a constant value minus an absolute signal value represented by the first digital data.

6. The digital-to-analog converter of claim 1 , wherein the data generation circuit is configured to generate the second digital data such that a temporal progression of a sum of an absolute signal value represented by the second digital data and an absolute signal value represented by the first digital data is constant.

7. The digital-to-analog converter of claim 1 , wherein the one or more second digital-to-analog converter cells are capable of driving a signal current that differs less than 50% from a signal current that can be driven by the one or more first digital-to-analog converter cells.

8. The digital-to-analog converter of claim 1 , wherein the second load couples the second output node to ground.

9. A data processing system, comprising:
a digital-to-analog converter according to claim 1 ;
a first load coupled to the first output node; and
a second load coupled to the second output node.

10. The data processing system of claim 9 , wherein load impedances presented to the digital-to-analog converter by the first load and the second load differ at maximum by a factor of 4.

11. The data processing system of claim 9 , wherein the digital-to-analog converter is integrated in a semiconductor die, and wherein at least one of the first load and the second load is arranged off the semiconductor die.

12. The data processing system of claim 9 , wherein the digital-to-analog converter is integrated in the same semiconductor die as the first load and the second load.

13. The data processing system of claim 9 , further comprising a power supply coupled to the one or more first digital-to-analog converter cells and the one or more second digital-to-analog converter cells for providing the supply current.

14. The data processing system of claim 9 , wherein the data processing system is a transmitter.

15. The data processing system of claim 14 , wherein the transmitter further comprises digital circuitry configured to supply the first digital data to the digital-to-analog converter.

16. The data processing system of claim 15 , wherein the digital circuitry is configured to generate the first digital data based on data to be wirelessly transmitted.

17. A base station, comprising:
a data processing system according to claim 9 ; and
at least one antenna element coupled to the digital-to-analog converter.

18. The base station of claim 17 , further comprising a receiver configured to receive a radio frequency receive signal from the antenna element.

19. A mobile device, comprising:
a data processing system according to claim 9 ; and
at least one antenna element coupled to the digital-to-analog converter.

20. The mobile device of claim 19 , further comprising a receiver configured to receive a radio frequency receive signal from the antenna element.

Assignees

• Intel Corp

Inventors

• Gruber Daniel
• Azadet Kameran
• Wang Yu-Shan
• Shin Hundo
• Clara Martin

Classifications

• H03M1/0614 Primary

  of harmonic distortion (H03M1/0617 takes precedence) · CPC title

• H04B1/0475

  with means for limiting noise, interference or distortion (H04B1/0483 takes precedence) · CPC title

• H04B1/1018

  noise filters connected between the power supply and the receiver · CPC title

• H03M1/66 Primary

  Digital/analogue converters ({H03M1/001 – } H03M1/10 take precedence) · CPC title

• H03M1/802

  using capacitors, e.g. neuron-mos transistors, charge coupled devices · CPC title