Dummy signal generation for reducing data dependent noise in digital-to-analog converters

Patent metadata

Field	Value
Publication number	US-9716508-B1
Application number	US-201615150833-A
Country	US
Kind code	B1
Filing date	May 10, 2016
Priority date	Mar 28, 2016
Publication date	Jul 25, 2017
Grant date	Jul 25, 2017

Abstract

Mechanisms for generating dummy signals for use in reducing data dependent noise in DACs are disclosed. Disclosed mechanisms differentiate between odd and even bits of a digital data signal to be converted and generate dummy signals by inverting some of these bits and leaving other bits as they are (i.e. including them in their non-inverted form). One dummy signal is generated as a sequence of bits that is the same as a sequence of bits of a data signal except that every odd bit of the data signal is inverted. An alternative dummy signal is generated as a sequence of bits that is the same as a sequence of bits of a data signal except that every even bit is inverted. Generating dummy signals in this manner eliminates the need to use calibration, feedback, or transition detectors, advantageously resulting in increased timing margins and substantial power savings over existing implementations.

First claim

What is claimed is:

1. A system for assisting in reducing data dependent noise in a digital-to-analog converter (DAC) unit of a DAC comprising a plurality of DAC units, the system comprising:
an arrangement configured to:
generate a time-series of dummy bits for a time-series of data bits to be provided to the DAC unit by, for each data bit, generating a dummy bit corresponding to the data bit as a bit having the same value as the data bit if the data bit is an even bit and as a bit having a value inverted from that of the data bit if the data bit is an odd bit, and
for each data bit, provide the data bit and the dummy bit corresponding to the data bit to the DAC unit in a single clock cycle.

2. The system according to claim 1 , wherein the arrangement is configured to separate the time-series of data bits into a first and a second half-rate time-series of data bits so that all odd data bits are included into the first half-rate time-series of data bits and all even data bits are included into the second half-rate time-series of data bits.

3. The system according to claim 2 , wherein generating the time-series of dummy bits comprises:
generating a first and a second half-rate time-series of dummy bits, where each dummy bit of the first half-rate time-series of dummy bits comprises a bit value that is an inversion of a corresponding data bit in the first half-rate time-series of data bits and each dummy bit of the second half-rate time-series of dummy bits comprises a bit value of a corresponding data bit in the second half-rate time-series of data bits.

4. The system according to claim 3 , wherein generating the time-series of dummy bits further comprises:
serializing the first and the second half-rate time-series of dummy bits into the time-series of dummy bits clocked at a full-rate clock.

5. The system according to claim 2 , further comprising a serializer for serializing the first and the second half-rate time-series of data bits into the time-series of data bits clocked at a full-rate clock.

6. The system according to claim 1 , wherein the arrangement is configured to separate the time-series of data bits into a first, a second, a third, and a fourth quarter-rate time-series of data bits so that every second odd data bit is included into the third quarter-rate time-series of data bits and all remaining odd data bits are included into the first quarter-rate time series of data bits, and so that every second even data bit is included into the fourth quarter-rate time-series of data bits and all remaining even data bits are included into the second quarter-rate time series of data bits.

7. The system according to claim 6 , wherein generating the time-series of dummy bits comprises:
generating a first, a second, a third, and a fourth quarter-rate time-series of dummy bits, where each dummy bit of the first quarter-rate time-series of dummy bits comprises a bit value that is an inversion of a corresponding data bit in the first quarter-rate time-series of data bits, each dummy bit of the second quarter-rate time-series of dummy bits comprises a bit value of a corresponding data bit in the second quarter-rate time-series of data bits, each dummy bit of the third quarter-rate time-series of dummy bits comprises a bit value that is an inversion of a corresponding data bit in the third quarter-rate time-series of data bits, and each dummy bit of the fourth quarter-rate time-series of dummy bits comprises a bit value of a corresponding data bit in the fourth quarter-rate time-series of data bits.

8. The system according to claim 7 , wherein generating the time-series of dummy bits further comprises:
serializing the first, the second, the third, and the fourth quarter-rate time-series of dummy bits into the time-series of dummy bits clocked at a full-rate clock.

9. The system according to claim 6 , further comprising a serializer for serializing the first, the second, the third, and the fourth quarter-rate time-series of data bits into the time-series of data bits clocked at a full-rate clock.

10. The system according to claim 1 , wherein the arrangement configured to generate a time-series of dummy bits comprises an inverter configured to invert the data bit if the data bit is determined to be the odd bit.

11. A system for assisting in reducing data dependent noise in a digital-to-analog converter (DAC) unit of a DAC comprising a plurality of DAC units, the system comprising:
an arrangement configured to:
generate a time-series of dummy bits for a time-series of data bits to be provided to the DAC unit by, for each data bit, generating a dummy bit corresponding to the data bit as a bit having the same value as the data bit if the data bit is an odd bit and as a bit having a value inverted from that of the data bit if the data bit is an even bit, and
for each data bit, provide the data bit and the dummy bit corresponding to the data bit to the DAC unit in a single clock cycle.

12. The system according to claim 11 , wherein the arrangement is configured to separate the time-series of data bits into a first and a second half-rate time-series of data bits so that all even data bits are included into the first half-rate time-series of data bits and all odd data bits are included into the second half-rate time-series of data bits.

13. The system according to claim 12 , wherein generating the time-series of dummy bits comprises:
generating a first and a second half-rate time-series of dummy bits, where each dummy bit of the first half-rate time-series of dummy bits comprises a bit value that is an inversion of a corresponding data bit in the first half-rate time-series of data bits and each dummy bit of the second half-rate time-series of dummy bits comprises a bit value of a corresponding data bit in the second half-rate time-series of data bits.

14. The system according to claim 13 , wherein generating the time-series of dummy bits further comprises:
serializing the first and the second half-rate time-series of dummy bits into the time-series of dummy bits clocked at a full-rate clock.

15. The system according to claim 12 , further comprising a serializer for serializing the first and the second half-rate time-series of data bits into the time-series of data bits clocked at a full-rate clock.

16. The system according to claim 11 , wherein the arrangement is configured to separate the time-series of data bits into a first, a second, a third, and a fourth quarter-rate time-series of data bits so that every second even data bit is included into the third quarter-rate time-series of data bits and all remaining even data bits are included into the first quarter-rate time series of data bits, and so that every second odd data bit is included into the fourth quarter-rate time-series of data bits and all remaining odd data bits are included into the second quarter-rate time series of data bits.

17. The system according to claim 16 , wherein generating the time-series of dummy bits comprises:
generating a first, a second, a third, and a fourth quarter-rate time-series of dummy bits, where each dummy bit of the first quarter-rate time-series of dummy bits comprises a bit value that is an inversion of a corresponding data bit in the first quarter-rate time-series of data bits, each dummy bit of the second quarter-rate time-series of dummy bits comprises a bit value of a corresponding data bit in the second quarter-rate time-series of data bits, each dummy bit of the third quarter-rate time-series of dummy bits comprises a bit value that is an inversion of a corresponding data bit in the third

Assignees

• Analog Devices Global

Inventors

• Zhang Lin

Classifications

• H03M1/66

  Digital/analogue converters ({H03M1/001 – } H03M1/10 take precedence) · CPC title

• H03M1/08 Primary

  of noise {(H03M1/0617 takes precedence)} · CPC title

• H03M1/0678

  using additional components or elements, e.g. dummy components · CPC title

• H03M1/687

  Segmented, i.e. the more significant bit converter being of the unary decoded type and the less significant bit converter being of the binary weighted type · CPC title

• H03M1/0863 Primary

  of switching transients, e.g. glitches · CPC title