Optimization of reference voltages in a non-volatile memory (NVM)

Patent metadata

Field	Value
Publication number	US-11901013-B2
Application number	US-202117541973-A
Country	US
Kind code	B2
Filing date	Dec 3, 2021
Priority date	Dec 3, 2020
Publication date	Feb 13, 2024
Grant date	Feb 13, 2024

Abstract

Method and apparatus for managing data in a non-volatile memory (NVM) of a storage device, such as a solid-state drive (SSD). Data are stored to and retrieved from a group of memory cells in the NVM using a controller circuit. The data are retrieved using a first set of read voltages which are applied to the respective memory cells. The first set of read voltages are accumulated into a history distribution, which is evaluated to arrive at a second set of read voltages based upon characteristics of the history distribution. A calibration operation is performed on the memory cells using the second set of read voltages as a starting point. A final, third set of read voltages is obtained during the calibration operation to provide error rate performance at an acceptable level. The third set of read voltages are thereafter used for subsequent read operations.

First claim

What is claimed is:

1. A method comprising:
storing data to a group of memory cells in a non-volatile memory (NVM);
reading the data from the group of memory cells by applying a first set of read voltages thereto;
accumulating the first set of read voltages into a history distribution;
calibrating the group of memory cells by selecting a second set of read voltages based on the history distribution, adjusting the second set of read voltages to arrive at a third set of read voltages, and using the third set of read voltages to subsequently read the data from the group of memory cells;
incorporating the third set of read voltages into the history distribution to form an updated history distribution that includes at least the first and third sets of read voltages; and
using the updated history distribution to schedule a subsequent data transfer operation upon the group of memory cells.

2. The method of claim 1 , wherein the first set of read voltages is characterized as multiple sets of read voltages having different voltage levels applied during each of a succession of read operations in which the data are read from the group of memory cells.

3. The method of claim 1 , wherein the accumulating step comprises arranging the first set of read voltages into a histogram, performing a curve fit operation upon the histogram, and selecting the second set of read voltages as a midpoint of the curve fit operation.

4. The method of claim 3 , wherein time-based weighting is applied to sample values within the respective first set of read voltages so that more recently utilized ones of the sample values receive a higher weighting and less recently utilized ones of the sample values receive a lower weighting.

5. The method of claim 3 , wherein the subsequent data transfer operation of the using step comprises a subsequent calibrating of the group of memory cells which is carried out at a time selected responsive to a shape of the curve fit operation.

6. The method of claim 1 , wherein each of the first and third sets of read voltages are identified during respective calibration operations upon the group of memory cells carried out at different times, each of the respective calibration operations comprising incrementally adjusting of read voltages to provide a resulting error rate that meets predetermined criteria.

7. The method of claim 1 , wherein the history distribution comprises sets of calibrated read voltages obtained during each of a succession of calibration operations upon the group of memory cells carried out over an operational interval, wherein at least one garbage collection operation involving an erasure of the group of memory cells has occurred during the operational interval.

8. The method of claim 1 , wherein the NVM is characterized as a NAND flash memory of a solid-state drive (SSD).

9. The method of claim 1 , wherein the subsequent data transfer operation of the using step comprises a garbage collection operation upon the group of memory cells.

10. The method of claim 1 , wherein the group of memory cells are arranged into a garbage collection unit (GCU), and the third set of read voltages are subsequently applied to read operations upon the GCU after a conclusion of the calibration step.

11. An apparatus comprising:
a non-volatile memory (NVM) comprising semiconductor memory cells;
a read circuit configured to read a programmed state of the memory cells responsive to application of a first of read voltages thereto; and
a read voltage manager circuit configured to perform a first calibration operation to generate the first set of read voltages, accumulate the first set of read voltages into a history distribution comprising additional sets of read voltages obtained by the read voltage manager circuit from a time-ordered sequence of previously performed calibration operations, select a second set of read voltages based on the history distribution, and perform a second calibration operation upon the memory cells by incrementally adjusting the second set of read voltages to arrive at a third set of read voltages that provide an error rate that meets predetermined criteria, the read circuit thereafter using the third set of read voltages during a subsequent read operation after a conclusion of the calibration operation, the read voltage manager circuit appending the third set of read voltages to the history distribution for use during subsequent calibration operations.

12. The apparatus of claim 11 , wherein the read voltage manager circuit determines a health status of a group of the memory cells responsive to a shape of the history distribution.

13. The apparatus of claim 12 , wherein each of the first, second and third read voltages respectively comprise read voltages of R 0 through Rn, wherein n is a plural number selected responsive to a total number of charge states stored by the memory cells of the NAND flash memory.

14. The apparatus of claim 12 , wherein each memory cell in the NAND flash memory stores multiple bits of data.

15. The apparatus of claim 11 , wherein the first set of read voltages is characterized as multiple sets of read voltages having different voltage levels applied during each of a succession of read operations in which the data are read from the group of memory cells.

16. The apparatus of claim 11 , wherein the read voltage manager arranges the first set of read voltages into a histogram, performs a curve fit operation upon the histogram, and selects the second set of read voltages as a midpoint of the curve fit operation.

17. The apparatus of claim 16 , wherein the read voltage manager further applies time-based weighting to sample values within the history distribution so that more recently utilized ones of the sample values receive a greater weighting and less recently utilized ones of the sample values receive a lower weighting.

18. The apparatus of claim 16 , wherein a garbage collection operation is performed on a selected grouping of the memory cells responsive to a shape of the history distribution curve fit operation.

19. A data storage device, comprising:
a flash memory comprising flash memory cells arranged into garbage collection units (GCUs) each allocated and erased as a unit;
a controller circuit configured to transfer user data sets between the GCUs and an external client device; and
a read voltage manager circuit configured to accumulate read voltages applied by the controller circuit to successfully retrieve the user data sets into a population distribution, to select an initial calibration set of read voltages based on a shape of the population distribution, to perform a calibration operation upon a calibration group of the memory cells to derive a final calibration set of read voltages based on the initial calibration set of read voltages, to implement subsequent read operations using the final calibration set of read voltages, and to add the final calibration set of read voltages to the population distribution for use during a subsequent calibration operation, the population distribution comprising previously obtained calibration sets of read voltages generated from corresponding calibration operations upon the flash memory cells prior to generation of the final calibration set of read voltages.

20. The data storage device of claim 19 , wherein the read voltage manager circuit further directs the controller circuit to perform a garbage collection operation upon a selected GCU responsive to a shape of a population distribution of read voltages used during read operation

Assignees

• Seagate Technology Llc

Inventors

• Secatch Stacey
• Henze Jonathan

Classifications

• G11C16/102 Primary

  External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators · CPC title

• G11C16/14

  Circuits for erasing electrically, e.g. erase voltage switching circuits · CPC title

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title

• G11C16/30

  Power supply circuits · CPC title

• G11C29/4401

  for self repair · CPC title