Data independent periodic calibration using per-pin VREF correction technique for single-ended signaling

Patent metadata

Field	Value
Publication number	US-9711239-B2
Application number	US-201615169156-A
Country	US
Kind code	B2
Filing date	May 31, 2016
Priority date	Nov 26, 2012
Publication date	Jul 18, 2017
Grant date	Jul 18, 2017

Abstract

A single-ended receiver includes an internal voltage generation circuit to set a first internal reference voltage (Vref). A model voltage generation circuit is configurable to receive an external reference voltage to be calibrated during an initial calibration. The model voltage generation circuit is configurable to track an offset value for voltage-temperature (VT) drift and the offset value is applied to the internal voltage generation circuit to calibrate the internal Vref during a periodic calibration of the single-ended receiver.

First claim

What is claimed is:

1. An apparatus comprising:
a first receiver to receive a first voltage reference (Vref) and a first data signal on a first pin of the apparatus;
a second receiver to receive a second Vref and a second data signal on a second pin of the apparatus;
a first circuit coupled to the first receiver, the first circuit to generate the first Vref based on a first digital value calibrated during an initial calibration of the apparatus;
a second circuit coupled to the second receiver, the second circuit to generate the second Vref based on a second digital value calibrated during the initial calibration;
a calibration controller coupled to the first circuit and the second circuit, the calibration controller to receive an external Vref on a third pin of the apparatus and to generate a third Vref based on a third digital value calibrated during the initial calibration, wherein the calibration controller, during a periodic calibration of the apparatus, is to:
determine an offset value representing a voltage-temperature (VT) drift in the third Vref;
apply the offset value to the first digital value to calibrate the first Vref; and
apply the offset value to the second digital value to calibrate the second Vref.

2. The apparatus of claim 1 , wherein the first circuit comprises a first digital-to-analog converter (DAC) and first logic coupled to the first DAC, wherein the second circuit comprises a second DAC and second logic coupled to the second DAC, and wherein the calibration controller comprises a third DAC and third logic coupled to the third DAC.

3. The apparatus of claim 2 , wherein the first DAC, the second DAC, and the third DAC are duplicate circuits.

4. The apparatus of claim 2 , wherein the first DAC comprises:
a resistor;
a plurality of current sources; and
a plurality of switches, each switch of the plurality of switches being coupled to one of the plurality of current sources and controlled by the first logic.

5. The apparatus of claim 2 , wherein the first DAC comprises:
a current source;
a plurality of resistors; and
a plurality of switches, each switch of the plurality of switches being coupled to one of the plurality of resistors and controlled by the first logic.

6. The apparatus of claim 2 , wherein the first DAC comprises:
a resistor coupled to a voltage source;
a plurality of resistors; and
a plurality of switches, each switch of the plurality of switches being coupled to one of the plurality of resistors and controlled by the first logic.

7. The apparatus of claim 1 , wherein the first receiver comprises:
a first amplifier to receive the first Vref from the first circuit and the first data signal on the first pin; and
first logic circuitry coupled to an output of the first amplifier, the first logic circuitry to calibrate the first receiver in the initial calibration using the external Vref and a signal pattern received on the first pin via a channel between the apparatus and a transmitter, and wherein the signal pattern is not received on the first pin during the periodic calibration.

8. The apparatus of claim 7 , wherein the first receiver further comprises:
a filter coupled to the first pin to receive the first data signal from the transmitter via the channel; and
a multiplexer coupled to the filter and to the first pin.

9. The apparatus of claim 7 , wherein the apparatus is a memory device.

10. The apparatus of claim 7 , wherein the apparatus is a memory controller.

11. A memory device comprising:
a first receiver to receive a first voltage reference (Vref) and a first data signal on a first pin of the memory device;
a second receiver to receive a second Vref and a second data signal on a second pin of the memory device;
a first voltage generation circuit coupled to the first receiver, the first voltage generation circuit to generate the first Vref based on a first digital value calibrated during an initial calibration of the memory device;
a second voltage generation circuit coupled to the second receiver, the second voltage generation circuit to generate the second Vref based on a second digital value calibrated during the initial calibration;
a calibration controller coupled to the first voltage generation circuit and the second voltage generation circuit, the calibration controller comprises a model voltage generation circuit to receive an external Vref on a third pin of the memory device and to generate a third Vref based on a third digital value calibrated during the initial calibration, wherein the calibration controller, during a periodic calibration of the memory device, is to:
determine an offset value representing a voltage-temperature (VT) drift in the third Vref;
apply the offset value to the first digital value to calibrate the first Vref; and
apply the offset value to the second digital value to calibrate the second Vref.

12. The memory device of claim 11 , wherein the first voltage generation circuit comprises a first digital-to-analog converter (DAC) and first logic coupled to the first DAC, wherein the second voltage generation circuit comprises a second DAC and second logic coupled to the second DAC, and wherein the model generation circuit comprises a third DAC and third logic coupled to the third DAC.

13. The memory device of claim 12 , wherein the first DAC, the second DAC, and the third DAC are duplicate circuits.

14. The memory device of claim 12 , wherein the third DAC comprises:
a resistor;
a plurality of current sources; and
a plurality of switches, each switch of the plurality of switches being coupled to one of the plurality of current sources and controlled by the first logic.

15. The memory device of claim 11 , wherein the first receiver comprises:
a first amplifier to receive the first Vref from the first voltage generation circuit and the first data signal on the first pin; and
first logic circuitry coupled to an output of the first amplifier, the first logic circuitry to calibrate the first receiver in the initial calibration using the external Vref and a signal pattern received on the first pin via a channel between the memory device and a memory controller, and wherein the signal pattern is not received on the first pin during the periodic calibration.

16. The memory device of claim 15 , wherein the first receiver further comprises:
a filter coupled to the first pin to receive the first data signal from the memory controller via the channel; and
a multiplexer coupled to the filter and to the first pin.

17. A method of calibrating a memory device comprising a calibration controller and a plurality of receivers, the method comprising:
determining a first digital value to calibrate a first circuit to generate a first voltage reference (Vref) during an initial calibration of the memory device;
receiving, by the calibration controller, an external Vref from a memory controller;
determining a third digital value to calibrate a calibration controller to generate a model Vref during the initial calibration using the external Vref;
determining an offset value to calibrate the model Vref during a periodic calibration; and
applying, by the calibration controller, the offset value to the first digital value to calibrate the first Vref during the periodic calibration.

18. The method of claim 17 , further comprising:
determining a second digital value to calibrate a second circuit to generate a second Vref during the initial calibration; and
applying, by the calibration controller, the offset value to the second digital value to calibrate

Assignees

• Rambus Inc

Inventors

• Venkatesan Pravin Kumar
• Prabhu Kashinath
• Shirasgaonkar Makarand
• Dettloff Wayne

Classifications

• H03M1/66

  Digital/analogue converters ({H03M1/001 – } H03M1/10 take precedence) · CPC title

• G11C11/4099

  Dummy cell treatment; Reference voltage generators · CPC title

• G11C29/023 Primary

  in clock generator or timing circuitry · CPC title

• G11C11/4076

  Timing circuits (for regeneration management G11C11/406) · CPC title

• G11C29/021

  in voltage or current generators · CPC title