Method for performing memory interface calibration in an electronic device, and associated apparatus and associated memory controller

Patent metadata

Field	Value
Publication number	US-9824728-B2
Application number	US-201414294094-A
Country	US
Kind code	B2
Filing date	Jun 2, 2014
Priority date	Dec 16, 2013
Publication date	Nov 21, 2017
Grant date	Nov 21, 2017

Abstract

A method for performing memory interface calibration in an electronic device, an associated apparatus, and an associated memory controller are provided, where the method includes: controlling a signal on a digital terminal of the memory controller to switch between a plurality of levels, wherein the digital terminal is coupled to a memory of the electronic device; and based on at least one detection result obtained from detecting the signal, calibrating a logical state of the signal to correspond to a level of the plurality of levels. More particularly, the memory controller may include a plurality of command terminals, a plurality of data terminals, and at least one clock terminal, which are used for coupling the memory controller to the memory. For example, the digital terminal may be a command terminal or a data terminal.

First claim

What is claimed is:

1. A method for performing memory interface calibration in an electronic device, the method being applied to a memory controller of the electronic device, the method comprising the steps of:
controlling a signal on a digital terminal of the memory controller to switch between a plurality of levels, wherein the digital terminal is coupled to a memory of the electronic device;
detecting a characteristic of the signal, on the digital terminal, received from the memory, wherein the characteristic comprises one or more of the amplitude, common mode level, or duty cycle of the second signal; and
by detecting the characteristic of the signal, calibrating a logical state of the signal to correspond to a level of the plurality of levels,
wherein the step of controlling the signal on the digital terminal of the memory controller to switch between the plurality of levels further comprises:
switching between a plurality of configurations of the memory controller to control the signal;
changing at least one control signal corresponding to at least one impedance component in a first impedance component set of a plurality of impedance components within the electronic device to switch between the plurality of configurations of the memory controller;
changing at least one control signal corresponding to at least one impedance component in a second impedance component set of the plurality of impedance components to switch between the plurality of configurations of the memory controller;
using a control signal corresponding to a first impedance component of the first impedance component set to selectively enable a conduction path between the digital terminal and a first node of the memory controller, wherein the conduction path between the digital terminal and the first node passes through the first impedance component of the first impedance component set; and
using a control signal corresponding to a second impedance component of the second impedance component set to selectively enable a conduction path between the digital terminal and a second node of the memory controller, wherein the conduction path between the digital terminal and the second node passes through the second impedance component of the second impedance component set.

2. The method of claim 1 , wherein the step of controlling the signal on the digital terminal of the memory controller to switch between the plurality of levels further comprises:
using a control signal corresponding to a third impedance component of the first impedance component set to selectively enable a conduction path between the digital terminal and the first node of the memory controller, wherein the conduction path between the digital terminal and the first node passes through the third impedance component of the first impedance component set.

3. The method of claim 1 , wherein the step of controlling the signal on the digital terminal of the memory controller to switch between the plurality of levels further comprises:
changing at least one control signal corresponding to at least one current source in a current source set of a plurality of current sources within the electronic device to switch between the plurality of configurations of the memory controller.

4. The method of claim 3 , wherein the step of controlling the signal on the digital terminal of the memory controller to switch between the plurality of levels further comprises:
using a control signal corresponding to a current source of the current source set to selectively enable a conduction path between the digital terminal and the first node of the memory controller, wherein the conduction path between the digital terminal and the first node passes through the current source of the current source set.

5. The method of claim 3 , wherein the step of controlling the signal on the digital terminal of the memory controller to switch between the plurality of levels further comprises:
changing at least one control signal corresponding to at least one current source in another current source set of the plurality of current sources to switch between the plurality of configurations of the memory controller.

6. The method of claim 5 , wherein the step of controlling the signal on the digital terminal of the memory controller to switch between the plurality of levels further comprises:
using a control signal corresponding to a current source of the current source set to selectively enable a conduction path between the digital terminal and the first node of the memory controller, wherein the conduction path between the digital terminal and the first node passes through the current source of the current source set; and
using a control signal corresponding to a current source of the other current source set to selectively enable a conduction path between the digital terminal and the second node of the memory controller, wherein the conduction path between the digital terminal and the second node passes through the current source of the other current source set.

7. The method of claim 1 , wherein the step of calibrating the logical state of the signal to correspond to the level of the plurality of levels further comprises:
based on at least one detection result obtained from detecting the signal, calibrating the logical state of the signal to correspond to the level of the plurality of levels and calibrating another logical state of the signal to correspond to another level of the plurality of levels.

8. The method of claim 1 , wherein the digital terminal is a data terminal of the memory controller; and the method further comprises:
sending at least one command through a command terminal of the memory controller to the memory to cause the signal to be output from the memory;
wherein switching the signal from one of the plurality of levels to another of the plurality of levels is controlled by the memory controller.

9. The method of claim 8 , wherein the step of sending the at least one command to the memory to cause the signal to be output from the memory further comprises:
using the at least one command to instruct the memory to control the signal to have a data pattern that alternatively switches between a logical value 0 and a logical value 1.

10. The method of claim 8 , wherein the step of sending the at least one command to the memory to cause the signal to be output from the memory further comprises:
using the at least one command to instruct the memory to control the signal to have a data pattern of a single logical value, rather than a data pattern that alternatively switches between different logical values.

11. The method of claim 1 , wherein the step of calibrating the logical state of the signal to correspond to the level of the plurality of levels further comprises:
based on at least one detection result obtained from detecting the signal, calibrating the logical state of the signal to correspond to the level of the plurality of levels;
wherein the at least one detection result comprises a duty cycle detection result; and
in a situation where a condition regarding the duty cycle detection result is satisfied, the logical state of the signal is calibrated to correspond to the level of the plurality of levels.

12. The method of claim 11 , wherein when the duty cycle detection result indicates that a duty cycle of the signal is equal to a predetermined percentage, the logical state of the signal is calibrated to correspond to the level of the plurality of levels.

13. The method of claim 11 , wherein when the duty cycle detection result indicates that a duty cycle of the signal falls within a range of a predetermined interval comprisin

Assignees

• Mediatek Inc

Inventors

• Chen Shang-Pin
• Hsieh Bo-Wei

Classifications

• G11C7/109 Primary

  Control signal input circuits · CPC title

• H04L25/0278

  Arrangements for impedance matching · CPC title

• G11C7/1084

  Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load · CPC title

• G06F13/1689

  Synchronisation and timing concerns (synchronisation on a memory bus G06F13/4234) · CPC title

• H03K19/018557

  Coupling arrangements; Impedance matching circuits · CPC title