Performing a cyclic redundancy checksum operation responsive to a user-level instruction

Patent metadata

Field	Value
Publication number	US-11899530-B2
Application number	US-202117359537-A
Country	US
Kind code	B2
Filing date	Jun 26, 2021
Priority date	Dec 23, 2005
Publication date	Feb 13, 2024
Grant date	Feb 13, 2024

Abstract

In one embodiment, the present invention includes a method for receiving incoming data in a processor and performing a checksum operation on the incoming data in the processor pursuant to a user-level instruction for the checksum operation. For example, a cyclic redundancy checksum may be computed in the processor itself responsive to the user-level instruction. Other embodiments are described and claimed.

First claim

What is claimed is:

1. A processor comprising:
a plurality of cores, wherein at least one of the cores comprises:
a cache;
a plurality of general-purpose registers; and
a plurality of execution units, including an integer execution unit and a single instruction multiple data (SIMD) execution unit, wherein at least one of the plurality of execution units comprises circuitry to:
perform a cyclic redundancy check (CRC) operation in response to one or more instructions executed in a 64-bit mode of operation, wherein the circuitry is to perform the CRC operation based on one of a plurality of data sizes, including a data size of 8-bits, 16-bits, 32-bits, and 64-bits, and wherein the one or more instructions are to indicate the data size to be used.

2. The processor of claim 1 , wherein the plurality of general-purpose registers are 64-bit general-purpose registers.

3. The processor of claim 1 , wherein said at least one of the plurality of execution units is to store a result of the CRC operation in a least significant 32-bits of a 64-bit general-purpose register and zeroes in a most significant 32-bits of the 64-bit general-purpose register.

4. The processor of claim 1 , wherein the plurality of execution units include a floating point unit.

5. The processor of claim 1 , wherein the at least one of the cores further comprises an address generation unit.

6. The processor of claim 1 , wherein the CRC operation is to be performed with a polynomial that does not correspond to 11EDC6F41H.

7. The processor of claim 1 , wherein the CRC operation is to be performed with a polynomial that corresponds to an Ethernet protocol.

8. The processor of claim 1 , wherein the CRC operation is to be performed with a selected one of a plurality of different possible polynomials.

9. A system comprising:
a memory controller;
a graphics engine; and
a multicore processor coupled to the memory controller and the graphics engine, the multicore processor comprising a plurality of cores, wherein at least one of the cores comprises:
a cache;
a plurality of general-purpose registers; and
a plurality of execution units, including an integer execution unit and a single instruction multiple data (SIMD) execution unit, wherein at least one of the plurality of execution units comprises circuitry to:
perform a cyclic redundancy check (CRC) operation in response to one or more instructions executed in a 64-bit mode of operation, wherein the circuitry is to perform the CRC operation based on one of a plurality of data sizes, including a data size of 8-bits, 16-bits, 32-bits, and 64-bits, and wherein the one or more instructions are to indicate the data size to be used.

10. The system of claim 9 , wherein the plurality of general-purpose registers are 64-bit general-purpose registers.

11. The system of claim 9 , wherein said at least one of the plurality of execution units is to store a result of the CRC operation in a least significant 32-bits of a 64-bit general-purpose register and zeroes in a most significant 32-bits of the 64-bit general-purpose register.

12. The system of claim 9 , wherein the CRC operation is to be performed with a polynomial that does not correspond to 11EDC6F41H.

13. The system of claim 9 , wherein the CRC operation is to be performed with a polynomial that corresponds to an Ethernet protocol.

14. The system of claim 9 , wherein the CRC operation is to be performed with a selected one of a plurality of different possible polynomials.

15. A system comprising:
a main memory; and
a multicore processor coupled to the main memory, the multicore processor comprising a plurality of cores, wherein at least one of the cores comprises:
a cache;
a plurality of general-purpose registers; and
a plurality of execution units, including an integer execution unit and a single instruction multiple data (SIMD) execution unit, wherein at least one of the plurality of execution units comprises circuitry to:
perform a cyclic redundancy check (CRC) operation in response to one or more instructions executed in a 64-bit mode of operation, wherein the circuitry is to perform the CRC operation based on one of a plurality of data sizes, including a data size of 8-bits, 16-bits, 32-bits, and 64-bits, and wherein the one or more instructions are to indicate the data size to be used.

16. The system of claim 15 , further comprising a data storage device, and wherein the plurality of general-purpose registers are 64-bit general-purpose registers.

17. The system of claim 15 , further comprising a communication device, and wherein said at least one of the plurality of execution units is to store a result of the CRC operation in a least significant 32-bits of a 64-bit general-purpose register and zeroes in a most significant 32-bits of the 64-bit general-purpose register.

18. The system of claim 15 , further comprising an audio input/output (I/O) device, and wherein the CRC operation is to be performed with a polynomial that does not correspond to 11EDC6F41H.

19. The system of claim 15 , wherein the CRC operation is to be performed with a polynomial that corresponds to an Ethernet protocol.

20. The system of claim 15 , wherein the CRC operation is to be performed with a selected one of a plurality of different possible polynomials.

Assignees

• Intel Corp

Inventors

• King Steven R
• Berry Frank L
• Kounavis Michael E

Classifications

• G06F9/30018

  Bit or string instructions · CPC title

• G06F11/1004 Primary

  to protect a block of data words, e.g. CRC or checksum (G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00) · CPC title

• G06F9/30003

  Arrangements for executing specific machine instructions · CPC title

• G06F9/30032

  Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE · CPC title

• G06F15/76

  Architectures of general purpose stored program computers (with program plugboard G06F15/08; multicomputers G06F15/16) · CPC title