Performing a cyclic redundancy checksum operation responsive to a user-level instruction

Patent metadata

Field	Value
Publication number	US-9645884-B2
Application number	US-201615009152-A
Country	US
Kind code	B2
Filing date	Jan 28, 2016
Priority date	Dec 23, 2005
Publication date	May 9, 2017
Grant date	May 9, 2017

Abstract

In one embodiment, the present invention includes a method for receiving incoming data in a processor and performing a checksum operation on the incoming data in the processor pursuant to a user-level instruction for the checksum operation. For example, a cyclic redundancy checksum may be computed in the processor itself responsive to the user-level instruction. Other embodiments are described and claimed.

First claim

What is claimed is:

1. A system comprising:
a processor comprising:
a plurality of cores, wherein at least one of the cores comprises:
a cache;
a plurality of general purpose registers; and
a plurality of execution units comprising a store data unit, an integer execution unit, a floating point execution unit, and a single instruction multiple data (SIMID) execution unit, wherein at least one of the plurality of execution units comprises logic to:
perform a cyclic redundancy check (CRC) operation in response to one or more CRC32 instructions to be executed in a 32-bit mode of operation or a 64-bit mode of operation, wherein the logic is to perform the CRC operation on one of a plurality of data sizes, including a data size of 8-bits, 16-bits, and 32-bits, and wherein the one or more CRC32 instructions are to indicate the data size on which to perform the CRC operation; and

an interface to a Peripheral Component Interconnect (PCI) Express bus.

2. The system of claim 1 , wherein each CRC32 instruction is referenced by a respective opcode to perform the CRC operation on each data size.

3. The system of claim 1 , wherein said at least one of the plurality of execution units, in response to a CRC32 instruction of the one or more CRC32instructions, is to perform a polynomial division using a polynomial represented by 11EDC6F41h.

4. The system of claim 1 , wherein the plurality of data sizes further comprises a data size of 64-bits in the 64-bit mode of operation.

5. The system of claim 1 , further comprising a memory interface logic to provide access to an external memory.

6. The system of claim 1 , further comprising:
a memory controller; and
a memory coupled with the memory controller.

7. The system of claim 1 , further comprising a memory coupled with the processor.

8. The system of claim 1 , further comprising a graphics engine.

9. The system of claim 1 , further comprising an audio input/output (I/O) interface coupled with the processor.

10. The system of claim 1 , further comprising a data storage device.

11. The system of claim 1 , further comprising a communication device.

12. A system comprising:
a processor comprising:
a store data unit;
a set of registers, including:
a first 32-bit register to store a first operand;
a second 32-bit register to store a second operand;
a first 64-bit register to store a third operand; and
a second 64-bit register to store a fourth operand; and

a plurality of execution units to perform exclusive-OR (XOR) operations on data of a configurable size responsive to instructions of an instruction set architecture (ISA) for the processor, the plurality of execution units including:
a first execution unit coupled to the first and second 32-bit registers to perform a first XOR operation on at least one bit of the first and second operands and to store a result of the first XOR operation in a first destination register responsive to a first instruction of the ISA; and
a second execution unit coupled to the first and second 64-bit registers to perform a second XOR operation on at least one bit of the third and fourth operands and to store a result of the second XOR operation in a second destination register responsive to a second instruction of the ISA; and

an interface to a Peripheral Component Interconnect (PCI) Express bus.

13. The system of claim 12 , wherein the first and second execution units are to respectively perform the first and second XOR operations in a same number of cycles.

14. The system of claim 12 , wherein the first destination register comprises one of the first and second 32-bit registers.

15. The system of claim 12 , wherein the second destination register comprises one of the first and second 64-bit registers.

16. The system of claim 12 , further comprising a memory interface logic to provide access to an external memory.

17. The system of claim 12 , further comprising a memory coupled with the processor.

18. The system of claim 12 , further comprising a graphics engine.

19. The system of claim 12 , further comprising a data storage device.

20. The system of claim 12 , further comprising an audio input/output (I/O) interface coupled with the processor.

21. A system comprising:
a processor comprising:
a plurality of cores, wherein at least one of the cores comprises:
a cache;
a plurality of general purpose registers; and
a plurality of execution units including a store data unit, an integer execution unit, a floating point execution unit, and a single instruction multiple data (SIMD) execution unit, wherein a given execution unit of the plurality of execution units is to:
perform a cyclic redundancy check (CRC) operation in response to a CRC32instruction to be executed in one of either a 32-bit mode of operation or a 64 -bit mode of operation, wherein the given execution unit is to perform the CRC operation on a data size that is capable of being any one of a plurality of data sizes including at least 8-bits, 16-bits, and 32-bits, and wherein the CRC32 instruction is to indicate the data size; and

an interface to a Peripheral Component Interconnect (PCI) Express bus.

22. The system of claim 21 , wherein the given execution unit, in response to the CRC32instruction, is to perform a polynomial division using a polynomial represented by 11EDC6F41h.

23. The system of claim 21 , wherein the plurality of data sizes includes a data size of 64-bits in the 64-bit mode of operation.

24. The system of claim 21 , further comprising:
a memory controller; and
a memory coupled with the memory controller.

25. The system of claim 21 , further comprising an audio input/output (I/O) interface coupled with the processor.

26. A system comprising:
a processor comprising:
a store data unit;
a plurality of registers, including:
a first 32-bit register to store a first operand;
a second 32-bit register to store a second operand;
a first 64-bit register to store a third operand; and
a second 64-bit register to store a fourth operand; and

a plurality of execution units to perform exclusive-OR (XOR) operations on data of a configurable size responsive to instructions of an instruction set architecture (ISA) for the processor, the plurality of execution units including:
a first execution unit coupled to the first and second 32-bit registers to perform a first XOR operation on at least one bit of the first and second operands and to store a result of the first XOR operation in a first destination register responsive to a first instruction of the ISA, wherein the first destination register is one of the first and second 32-bit registers; and
a second execution unit coupled to the first and second 64-bit registers to perform a second XOR operation on at least one bit of the third and fourth operands and to store a result of the second XOR operation in a second destination register responsive to a second instruction of the ISA, wherein the second destination register is one of the first and second 64-bit registers;

an interface to a Peripheral Component Interconnect (PCI) Express bus; and
a memory interface logic to provide access to a memory.

27. The system of claim 26 , further comprising a memory coupled with the memory interface logic.

Assignees

• Intel Corp

Inventors

• King Steven R
• Berry Frank L
• Kounavis Michael E

Classifications

• H03M13/093

  CRC update after modification of the information word · CPC title

• H03M13/09

  Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit · CPC title

• G06F15/76

  Architectures of general purpose stored program computers (with program plugboard G06F15/08; multicomputers G06F15/16) · CPC title

• G06F9/30003

  Arrangements for executing specific machine instructions · CPC title

• H03M13/00

  Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes (error detection or error correction for analogue/digital, digital/analogue or code conversion H03M1/00 – H03M11/00; specially adapted for digital computers G06F11/08; for information storage based on relative movement between record carrier and transducer G11B, e.g. G11B20/18; for static stores G11C) · CPC title