Performing a cyclic redundancy checksum operation responsive to a user-level instruction

Patent metadata

Field	Value
Publication number	US-11048579-B2
Application number	US-201916538812-A
Country	US
Kind code	B2
Filing date	Aug 12, 2019
Priority date	Dec 23, 2005
Publication date	Jun 29, 2021
Grant date	Jun 29, 2021

Abstract

In one embodiment, the present invention includes a method for receiving incoming data in a processor and performing a checksum operation on the incoming data in the processor pursuant to a user-level instruction for the checksum operation. For example, a cyclic redundancy checksum may be computed in the processor itself responsive to the user-level instruction. Other embodiments are described and claimed.

First claim

What is claimed is:

1. A processor comprising:
a cache;
a plurality of 64-bit registers including a first 64-bit register to store 64-bits of source data and a second 64-bit register to store a 32-bit initial value in bits [31:0]; and
execution circuitry coupled with the first and second 64-bit registers, the execution circuitry, responsive to a 32-bit cyclic redundancy check (CRC32) instruction of an instruction set architecture of the processor, to:
perform CRC32 computations on the 64-bits of source data and the 32-bit initial value according to a polynomial value of 11EDC6F41H; and
store a result of the CRC32 computations in bits [31:0] of a 64-bit destination register and zeroes in bits [63:32] of the 64-bit destination register.

2. The processor of claim 1 , wherein the CRC32 computations comprise incremental CRC32 computations on a plurality of portions of the 64-bits of source data.

3. The processor of claim 1 , wherein the CRC32 instruction is a user-level instruction.

4. The processor of claim 1 , further comprising:
a floating point unit;
a reorder buffer (ROB);
a load buffer; and
a store buffer.

5. The processor of claim 1 , further comprising a memory controller.

6. A processor comprising:
a cache;
a plurality of 64-bit registers including a first 64-bit register to store source data and a second 64-bit register to store a 32-bit initial value in bits [31:0]; and
an execution circuitry coupled with the first and second 64-bit registers, the execution circuitry, responsive to a 32-bit cyclic redundancy check (CRC32) instruction of an instruction set architecture of the processor, to:
perform CRC32 computations on the source data and the 32-bit initial value according to a polynomial value of 11EDC6F41H; and
store a result of the CRC32 computations in a destination register.

7. The processor of claim 6 , wherein the source data is one of 8-bits, 16-bits, 32-bits, and 64-bits.

8. The processor of claim 7 , wherein the source data is 64-bits, wherein destination register is a 64-bit destination register, and wherein the execution circuitry is to store the result in bits [31:0] of the 64-bit destination register and zeroes in bits [63:32] of the 64-bit destination register.

9. The processor of claim 7 , wherein the source data is 64-bits, and wherein the CRC32 computations comprise incremental CRC32 computations on a plurality of portions of the 64-bits of source data.

10. The processor of claim 6 , wherein the CRC32 instruction is a user-level instruction.

11. The processor of claim 6 , further comprising:
a floating point unit;
a reorder buffer (ROB);
a load buffer; and
a store buffer.

12. The processor of claim 6 , further comprising a memory controller.

13. A system comprising:
a processor, the processor comprising:
a cache;
a plurality of 64-bit registers including a first 64-bit register to store 64-bits of source data and a second 64-bit register to store a 32-bit initial value in bits [31:0]; and
an execution unit coupled with the first and second 64-bit registers, the execution unit, responsive to a 32-bit cyclic redundancy check (CRC32) instruction of an instruction set architecture of the processor, to:
perform CRC32 computations on the 64-bits of source data and the 32-bit initial value based on a polynomial value of 11EDC6F41H; and
store a result of the CRC32 computations in bits [31:0] of a 64-bit destination and zeroes in bits [63:32] of the 64-bit destination; and

a data storage device coupled to the processor.

14. The system of claim 13 , wherein the CRC32 computations comprise incremental CRC32 computations on a plurality of portions of the 64-bits of source data.

15. The system of claim 13 , wherein the CRC32 instruction is a user-level instruction.

16. The system of claim 13 , wherein the processor comprises:
a floating point unit;
a reorder buffer (ROB);
a load buffer; and
a store buffer.

17. The system of claim 13 , wherein the processor comprises a memory controller.

18. The system of claim 17 , further comprising a memory coupled to the memory controller.

19. The system of claim 13 , wherein the system is to use the result to process a storage protocol.

20. The processor of claim 1 , wherein the CRC32 computations comprise incremental CRC32 computations on a plurality of portions of the 64-bits of source data, wherein the CRC32 instruction is a user-level instruction, wherein the processor further comprises a reorder buffer (ROB).

Assignees

• Intel Corp

Inventors

• King Steven R
• Berry Frank L
• Kounavis Michael E

Classifications

• G06F9/30018

  Bit or string instructions · CPC title

• H03M13/093

  CRC update after modification of the information word · CPC title

• H03M13/096

  Checksums · CPC title

• G06F9/30003

  Arrangements for executing specific machine instructions · CPC title

• G06F15/76

  Architectures of general purpose stored program computers (with program plugboard G06F15/08; multicomputers G06F15/16) · CPC title