Vertical non-volatile memory devices having a multi-stack structure with enhanced photolithographic alignment characteristics

Patent metadata

Field	Value
Publication number	US-11895827-B2
Application number	US-202117469469-A
Country	US
Kind code	B2
Filing date	Sep 8, 2021
Priority date	Dec 22, 2020
Publication date	Feb 6, 2024
Grant date	Feb 6, 2024

Abstract

A vertical-type nonvolatile memory device has a multi-stack structure with reduced susceptibility to mis-alignment of a vertical channel layer. This nonvolatile memory device includes: (i) a main chip area including a cell area and an extension area arranged to have a stepped structure, with the cell area and the extension area formed in a multi-stack structure, and (ii) an outer chip area, which surrounds the main chip area and includes a step key therein. The main chip area includes a first layer on a substrate and a second layer on the first layer. A lower vertical channel layer is arranged in the first layer. The step key includes an alignment vertical channel layer, and a top surface of the alignment vertical channel layer is lower than a top surface of the lower vertical channel layer.

First claim

What is claimed is:

1. A nonvolatile memory device, comprising:
a substrate having a main chip area thereon, said main chip area including a first memory cell layer and second memory cell layer stacked on the first memory cell layer, said first memory cell layer including a first vertical channel layer, a first interlayer insulating layer, and a first gate electrode layer, and said second memory cell layer including: (i) a second vertical channel layer vertically aligned with the first vertical channel layer, (ii) a second interlayer insulating layer, and (iii) a second gate electrode layer;
an outer chip area on the substrate, which at least partially surrounds the main chip area in a portion of the substrate devoid of active devices, said outer chip layer including a step key therein that comprises an alignment vertical channel layer formed concurrently with the first vertical channel layer, said alignment vertical channel layer having a top surface that is recessed relative to the top surface of the first vertical channel layer after the first vertical channel layer is formed;
an electrically insulating layer on the second memory cell layer; and
a mold structure on the alignment vertical channel layer, said mold structure having a contoured upper surface that: (i) meets an upper surface of the electrically insulating layer, and (ii) sufficiently replicates a contoured upper surface of the outer chip area caused, at least in part, by the recessed top surface of the alignment vertical channel layer that the contoured upper surface of the mold structure can be used to support photolithographic alignment of the second vertical channel layer to the first vertical channel layer when channel layer holes are etched through the electrically insulating layer, the second interlayer insulating layer, and the second gate electrode layer;
wherein the step key further comprises an electrically insulating recessed portion, which abuts the alignment vertical channel layer; and
wherein the alignment vertical channel layer protrudes from the electrically insulating recessed portion such that the top surface of the alignment vertical channel layer is spaced farther from an underlying surface of the substrate relative to a top surface of the electrically insulating recessed portion.

2. The nonvolatile memory device of claim 1 , wherein the alignment vertical channel layer and the first vertical channel layer comprise the same material.

3. The nonvolatile memory device of claim 1 , wherein the mold structure comprises an alternating arrangement of a plurality of interlayer insulating layers and a plurality of sacrificial layers.

4. The nonvolatile memory device of claim 3 , wherein the alignment vertical channel layer and the first vertical channel layer comprise polycrystalline silicon.

5. A nonvolatile memory device, comprising:
a substrate having a main chip area thereon, said main chip area including a first memory cell layer and second memory cell layer stacked on the first memory cell layer, said first memory cell layer including a first vertical channel layer, a first interlayer insulating layer, and a first gate electrode layer, and said second memory cell layer including: (i) a second vertical channel layer vertically aligned with the first vertical channel layer, (ii) a second interlayer insulating layer, and (iii) a second gate electrode layer;
an outer chip area on the substrate, which at least partially surrounds the main chip area in a portion of the substrate devoid of active devices, said outer chip layer including a first photolithographic alignment key therein that comprises an alignment vertical channel layer with a top surface that is recessed relative to the top surface of the first vertical channel layer; and
a mold structure on the first photolithographic alignment key, said mold structure having a contoured upper surface thereon, which sufficiently replicates upper surface contours of the first photolithographic alignment key that the contoured upper surface operates as a second photolithographic alignment key during formation of the second vertical channel layer;
wherein the first photolithographic alignment key further comprises an electrically insulating recessed portion, which abuts the alignment vertical channel layer; and
wherein the alignment vertical channel layer protrudes from the electrically insulating recessed portion such that the top surface of the alignment vertical channel layer is spaced farther from an underlying surface of the substrate relative to a top surface of the electrically insulating recessed portion.

6. The nonvolatile memory device of claim 5 , wherein the mold structure comprises an alternating arrangement of a plurality of interlayer insulating layers and a plurality of sacrificial layers.

7. The nonvolatile memory device of claim 5 , wherein the alignment vertical channel layer and the first vertical channel layer comprise the same material.

8. The nonvolatile memory device of claim 7 , wherein the alignment vertical channel layer and the first vertical channel layer comprise polycrystalline silicon.

9. The nonvolatile memory device of claim 6 , wherein the alternating arrangement of the plurality of interlayer insulating layers and the plurality of sacrificial layers are stacked on the alignment vertical channel layer.

10. A vertical type nonvolatile memory device comprising:
a main chip area comprising a cell area and an extension area extending from the cell area in a first direction and arranged to have a stepped structure, wherein the cell area and the extension area are formed in a multi-stack structure; and
an outer chip area, which surrounds the main chip area and in which a step key is arranged, wherein
the main chip area comprises a first layer arranged on a substrate and a second layer on the first layer, a lower vertical channel layer connected to the substrate is arranged in the first layer, and
the step key comprises an alignment vertical channel layer corresponding to the lower vertical channel layer, and a top surface of the alignment vertical channel layer is lower than the top surface of the lower vertical channel layer;
wherein the outer chip area resides in a portion of the substrate devoid of active devices;
wherein the step key further comprises a recessed portion that is a portion other than the alignment vertical channel layer, and
the top surface of the alignment vertical channel layer is higher than a bottom surface of the recessed portion by a first step.

11. The vertical type nonvolatile memory device of claim 10 , wherein the outer chip area comprises the step key corresponding to the first layer and a key outer area and a mold structure corresponding to the second layer and covering the step key and the key outer area,
the mold structure comprises a plurality of sacrificial layers and interlayer insulating layers, which are alternately stacked, and
a top surface of the key outer area is higher than the top surface of the alignment vertical channel layer and has a substantially the same height as the top surface of the lower vertical channel layer.

12. The vertical type nonvolatile memory device of claim 11 , wherein a curve corresponding to the first step is formed on a top surface of the mold structure, and
the step key and the curvature are used in alignment of the lower vertical channel layer and an upper vertical channel layer of the second layer in the main chip area.

13. The vertical type nonvolatile memory device of claim 10 , further comprising an outer peri area between the extension area and the outer chip area in the first direction, wherein
the outer peri area is

Assignees

• Samsung Electronics Co Ltd

Inventors

• Chung Giyong
• Kwon Youngjin
• Eun Dongseog

Classifications

• H10W46/00

  Marks applied to devices, e.g. for alignment or identification · CPC title

• H10P54/00

  Cutting or separating of wafers, substrates or parts of devices · CPC title

• H10B12/395 Primary

  the transistor being vertical · CPC title

• H10B12/0383

  wherein the transistor is vertical · CPC title

• H10B12/50

  Peripheral circuit region structures · CPC title