Semiconductor devices having dummy patterns and methods of fabricating the same

Patent metadata

Field	Value
Publication number	US-9748257-B2
Application number	US-201514962237-A
Country	US
Kind code	B2
Filing date	Dec 8, 2015
Priority date	Dec 8, 2014
Publication date	Aug 29, 2017
Grant date	Aug 29, 2017

Abstract

Provided are semiconductor devices and methods of fabricating the same. The semiconductor devices may include a substrate with a cell region and a peripheral region, a gate stack including gates stacked on the cell region of the substrate. At least one edge portion of the gate stack may have a staircase structure. The semiconductor devices may also include a channel that extend through the gate stack and is enclosed by a memory layer and at least two dummy patterns on the substrate. The at least two dummy patterns may be spaced apart from the gate stack and may be spaced apart from each other.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a substrate including a cell region and a peripheral region;
a gate stack including a plurality of gates stacked on the cell region of the substrate, at least one edge portion of the gate stack having a staircase structure;
a channel extending through the gate stack and being enclosed by a memory layer; and
at least two dummy patterns spaced apart from the gate stack on the substrate, the at least two dummy patterns being spaced apart from each other,
wherein the peripheral region comprises at least one transistor provided on the substrate, and
wherein the at least two dummy patterns have substantially the same structure as the at least one transistor.

2. The semiconductor device of claim 1 , wherein the cell region comprises:
a cell array region, on which the gate stack is provided; and
a cell end region between the cell array region and the peripheral region,
wherein the at least two dummy patterns are provided on the cell end region.

3. The semiconductor device of claim 1 , further comprising a trench insulating layer in the substrate between the at least two dummy patterns.

4. The semiconductor device of claim 1 , wherein the at least two dummy patterns
comprise two first dummy patterns on the substrate, the two first dummy patterns are spaced apart from the at least one edge portion of the gate stack having the staircase structure by a first distance, and the two first dummy patterns are spaced apart from each other by a first space, and
wherein the semiconductor device further comprises two second dummy patterns on the substrate, the two second dummy patterns are spaced apart from the at least one edge portion of the gate stack having the staircase structure by a second distance that is greater than the first distance, and the two second dummy patterns are spaced apart from each other by a second space.

5. The semiconductor device of claim 4 , wherein the second space is less than the first space.

6. A semiconductor device, comprising:
a substrate including a cell array region and a peripheral region;
a gate stack provided on the cell array region of the substrate, the gate stack including a plurality of word lines which are arranged along a channel extending between at least two selection lines that are spaced apart from each other and at least one edge portion having a staircase structure;
a bit line provided on the gate stack and electrically connected to the channel;
at least one transistor provided on the peripheral region of the substrate and covered with an insulating layer; and
at least one pair of first dummy patterns provided between the gate stack and the at least one transistor and spaced apart from each other on the substrate,
wherein the at least one pair of first dummy patterns comprises a gate insulating layer on the substrate, a gate on the gate insulating layer, and a spacer on a side surface of the gate.

7. The semiconductor device of claim 6 , wherein the substrate further comprises a cell end region comprising a portion of the cell array region and being connected to the peripheral region, and
the at least one pair of first dummy patterns are provided on the cell end region.

8. The semiconductor device of claim 6 , further comprising at least one pair of second dummy patterns provided on the substrate and spaced apart from each other,
wherein a first space between the at least one pair of first dummy patterns is equal to or different from a second space between the at least one pair of second dummy patterns.

9. The semiconductor device of claim 8 , wherein the at least one pair of first dummy patterns are disposed adjacent to the gate stack, the at least one pair of second dummy patterns are disposed adjacent to the at least one transistor, and the second space is less than the first space.

10. The semiconductor device of claim 6 , further comprising a trench insulating layer in the substrate between the at least one pair of first dummy patterns.

11. A semiconductor device comprising:
a gate stack and a peripheral transistor on a substrate;
a first dummy pattern between the gate stack and the peripheral transistor on the substrate; and
a second dummy pattern disposed between the first dummy pattern and the peripheral transistor,
wherein the first dummy pattern is spaced apart from the gate stack and the peripheral transistor,
wherein the gate stack includes a staircase structure at one sidewall thereof adjacent to the first dummy pattern,
wherein the first dummy pattern includes at least two first key patterns spaced apart from each other by a first spacing, and
wherein the second dummy pattern includes at least two second key patterns spaced apart from each other by a second spacing that is less than the first spacing.

12. The semiconductor device of claim 11 , wherein the substrate comprises:
a cell region on which the gate stack is provided;
a peripheral region on which the peripheral transistor is provided; and
a cell end region between the cell region and the peripheral region, the first dummy pattern being provided on the cell end region,
wherein the staircase structure of the gate stack has a downhill slope along a first direction toward the cell end region from the cell region.

13. The semiconductor device of claim 12 , wherein the first dummy pattern extends along a second direction, the second direction crossing the first direction.

14. The semiconductor device of claim 13 , wherein the cell region comprises at least one bit line electrically connected to the gate stack, and the at least one bit line extends along the second direction.

15. The semiconductor device of claim 11 , wherein the at least two first key patterns comprise at least two dummy transistors, and the at least two dummy transistors extend parallel to each other.

16. The semiconductor device of claim 11 , wherein the at least two first key patterns comprise at least two insulating blocks, and the at least two insulating blocks extend parallel to each other.

17. The semiconductor device of claim 11 , wherein each of the at least two first key patterns comprises a gate insulating layer on the substrate, a gate on the gate insulating layer, and a spacer on a side surface of the gate.

18. The semiconductor device of claim 11 , wherein each of the at least two first key patterns has substantially the same structure as the peripheral transistor.

19. The semiconductor device of claim 11 , further comprising a trench insulating layer in the substrate between the at least two first key patterns.

20. The semiconductor device of claim 6 , wherein each of the at least one pair of first dummy patterns has substantially the same structure as the at least one transistor provided on the peripheral region.

Assignees

• Lee Jaehan
• Jung Won-Seok
• Joo Kyungjoong
• Samsung Electronics Co Ltd

Inventors

• Lee Jaehan
• Jung Won-Seok
• Joo Kyungjoong

Classifications

• H01L27/11565 Primary

  Electricity · mapped topic

• H01L27/11575

  Electricity · mapped topic

• H01L27/11524

  Electricity · mapped topic

• H01L27/11582

  Electricity · mapped topic

• H01L27/11556

  Electricity · mapped topic