Timing precision maintenance with reduced power during system sleep

Patent metadata

Field	Value
Publication number	US-11895588-B2
Application number	US-202117385536-A
Country	US
Kind code	B2
Filing date	Jul 26, 2021
Priority date	Aug 5, 2020
Publication date	Feb 6, 2024
Grant date	Feb 6, 2024

Abstract

Embodiments of the present disclosure provide systems and methods for maintaining timing precision in different operating modes of a device (e.g., a wireless node). A timing circuit may switch clock signals between two different modes (e.g., high power and low power) while preserving timing precision. In a high-power mode, the timing circuit may provide a high frequency clock signal, and in a lower-power mode, it may provide a low frequency clock signal. Moreover, the switching between the different clock signals may be synchronized to select edges of the low frequency clock signal.

First claim

The invention claimed is:

1. A clock circuit comprising:
a clock to generate a first clock signal having a first frequency;
a clock divider to divide the first clock signal to generate a second clock signal output at a second frequency, wherein the first frequency is higher than the second frequency;
a multiplexor to receive the first and second clock signals as inputs;
a controller coupled to the multiplexor to control the multiplexor to output the first clock signal during a first mode and to output the second clock signal during a second mode, wherein switching directly between the first clock signal and second clock signal by the multiplexor is performed based on a select edge of the second clock signal; and
a system time counter coupled to the multiplexor to maintain a system time count, wherein the system counter configured to increment the system time count based on the first clock signal during the first mode and to increment the system time count based on the second clock signal during the second mode.

2. The clock circuit of claim 1 , wherein in response to a command to switch from the first mode to the second mode, the controller is configured to switch the multiplexor output from the first clock signal to the second clock signal at the select edge of the second clock signal.

3. The clock circuit of claim 1 , wherein in response to a command to switch from the second mode to the first mode, the controller is configured to switch the multiplexor output from the second clock signal to the first clock signal at the select edge of the second clock signal.

4. The clock circuit of claim 1 , further including:
a clock gate coupled to the first clock signal output to connect and disconnect the first clock signal to the multiplexor.

5. The clock circuit of claim 4 ,
wherein the clock gate and the divider are located spatially close to the clock, wherein the clock includes a crystal oscillator.

6. The clock circuit of claim 1 , wherein the clock divider is configured to generate a plurality of second clock signals, each second clock signal oscillating at a different frequency.

7. A method to maintain timing between different modes, the method comprising:
receiving a command to switch from a first power mode to a second power mode;
in response to receiving the command, detecting a next specified edge of a low frequency clock signal of a set of clock signals;
switching directly to a clock signal corresponding to the second power mode at the detected edge of the low frequency clock;
maintaining a system time count based on a second clock signal corresponding to the first power mode; and
in response to switching to the clock signal corresponding to the second power mode, maintaining the system time count based on the clock signal corresponding to the second power mode.

8. The method of claim 7 , wherein the first power mode is a high-power mode, the second power mode is a low-power mode, and the clock signal corresponding to the second power mode is the low frequency clock signal.

9. The method of claim 8 , further comprising:
in response to switching to the clock signal corresponding to the second power mode, blocking a second clock signal corresponding to the first power mode.

10. The method of claim 7 , wherein the first mode is a low-power mode, the second power mode is a high-power mode, and the clock signal corresponding to the second power is a high frequency clock signal.

11. The method of claim 10 , further comprising:
prior to switching to the clock signal corresponding to the second power mode, enabling the high frequency clock signal.

12. The method of claim 10 , further comprising:
using the high frequency clock signal to generate the low frequency clock signal.

13. A device to maintain timing between modes, the device comprising:
a radio interface to communicate with another device; and,
a clock circuit, comprising:
a clock to generate a first clock signal having a first frequency;
a clock divider to divide the first clock signal to generate a second clock signal at a second frequency, wherein the first frequency is higher than the second frequency;
a multiplexor to receive the first and second clock signals as inputs; and
a controller coupled to multiplexor to control the multiplexor to output the first clock signal during a first mode and to output the second clock signal during a second mode, wherein switching directly between the first clock signal and second clock signal by the multiplexor is performed based on a select edge of the second clock signal; and
a system time counter coupled to the multiplexor to maintain a system time count, wherein the system counter configured to increment the system time count based on the first clock signal during the first mode and to increment the system time count based on the second clock signal during the second mode.

14. The device of claim 13 , wherein in response to a command to switch from the first mode to the second mode, the controller is configured to switch the multiplexor output from the first clock signal to the second clock signal at the select edge of the second clock signal.

15. The device of claim 13 , wherein in response to a command to switch from the second mode to the first mode, the controller is configured to switch the multiplexor output from the second clock signal to the first clock signal at the select edge of the second clock signal.

16. The device of claim 13 , further comprising
a clock gate coupled to the clock to connect and disconnect the first clock signal to the multiplexor.

Assignees

• Analog Devices Inc

Inventors

• Warneke Brett
• Ng Gary Wayne
• Lemkin Mark Alan

Classifications

• G06F1/08

  Clock generators with changeable or programmable clock frequency · CPC title

• H04W52/0229 Primary

  where the received signal is a wanted signal · CPC title

• H04J3/0667

  Bidirectional timestamps, e.g. NTP or PTP for compensation of clock drift and for compensation of propagation delays (arrangements for monitoring round trip delays in packet switching networks H04L43/0864) · CPC title

• H04W56/001

  Synchronization between nodes · CPC title

• H04W56/0035

  detecting errors in frequency or phase · CPC title