Apparatuses, methods, and systems for glitch-free clock switching

Patent metadata

Field	Value
Publication number	US-2016269034-A1
Application number	US-201514657225-A
Country	US
Kind code	A1
Filing date	Mar 13, 2015
Priority date	Mar 13, 2015
Publication date	Sep 15, 2016
Grant date	—

Abstract

Aspects disclosed in the detailed description include apparatuses, methods, and systems for glitch-free clock switching. In this regard, in one aspect, an electronic circuit is switched from a lower-frequency reference clock to a higher-frequency reference clock. An oscillation detection logic is configured to determine the stability of the higher-frequency reference clock prior to switching the electronic circuit to the higher-frequency reference clock. The oscillation detection logic derives a sampled clock signal from the higher-frequency reference clock, wherein the sampled clock signal has a slower frequency than the lower-frequency reference clock. The oscillation detection logic then compares the sampled clock signal against the lower-frequency reference clock to determine the stability of the higher-frequency reference clock. By deterministically detecting stability of a reference clock prior to switching to the reference clock, it is possible to avoid premature switching to an unstable reference clock, thus providing glitch-free clock switching in the electronic circuit.

First claim

What is claimed is:

1 . A clock switching control circuit, comprising:
a power control logic configured to switch an electronic circuit from a first reference clock signal associated with a first operation mode to a second reference clock signal associated with a second operation mode; and an oscillation detection logic coupled to the power control logic, wherein the oscillation detection logic is configured to:
determine stability of the second reference clock signal based on the first reference clock signal; and
provide a clock stability indication to the power control logic if the second reference clock signal is determined stable;
wherein the power control logic is configured to control the electronic circuit to switch from the first reference clock signal to the second reference clock signal in response to receiving the clock stability indication.

2 . The clock switching control circuit of claim 1 , wherein the first operation mode is a low-power operation mode associated with the first reference clock signal and the second operation mode is a normal-power operation mode associated with the second reference clock signal.

3 . The clock switching control circuit of claim 1 , wherein:
the first reference clock signal is a lower-frequency reference clock; the second reference clock signal is a higher-frequency reference clock; and the first reference clock signal is slower than the second reference clock signal.

4 . The clock switching control circuit of claim 1 , wherein the power control logic is provided in a physical coding sublayer (PCS) in the electronic circuit.

5 . The clock switching control circuit of claim 1 , wherein the oscillation detection logic comprises:
a ripple divider comprising a plurality of ripple counters disposed according to a serial arrangement, wherein the ripple divider is configured to derive a plurality of divided clock signals from the second reference clock signal; and a sampling logic coupled to the ripple divider to receive the plurality of divided clock signals, wherein the sampling logic is configured to:
programmably select a sampled clock signal among the plurality of divided clock signals based on the first reference clock signal; and
provide one or more edge detect indications of the sampled clock signal to a sampling comparison logic;
wherein the sampling comparison logic is configured to:
for each of the one or more edge detect indications of the sampled clock signal:
determine a frequency differential between the edge detect indication and the first reference clock signal;
compare the frequency differential against a predetermined frequency match threshold; and
provide a frequency match indication to a sampling decision logic if the frequency differential is less than the predetermined frequency match threshold;

wherein the sampling decision logic is configured to provide the clock stability indication to the power control logic if a count of the frequency match indication received consecutively from the sampling comparison logic is greater than or equal to a predetermined clock stability threshold.

6 . The clock switching control circuit of claim 5 , wherein the sampled clock signal is at least four (4) times slower than the first reference clock signal.

7 . The clock switching control circuit of claim 5 , wherein each of the plurality of ripple counters is a decrementing counter.

8 . The clock switching control circuit of claim 1 , wherein the power control logic enables the oscillation detection logic by providing a clock stability detection request to the oscillation detection logic.

9 . The clock switching control circuit of claim 8 , wherein the power control logic is further configured to:
start an oscillation detection timeout timer when providing the clock stability detection request to the oscillation detection logic; and switch the electronic circuit from the first reference clock signal to the second reference clock signal if the clock stability indication is not received at expiration of the oscillation detection timeout timer.

10 . The clock switching control circuit of claim 1 , wherein the power control logic is further configured to switch the electronic circuit from the second reference clock signal associated with the second operation mode to the first reference clock signal associated with the first operation mode.

11 . A clock switching control circuit, comprising:
a means for controlling a power mode configured to switch an electronic circuit from a first reference clock signal associated with a first operation mode to a second reference clock signal associated with a second operation mode; and a means for detecting a clock stability coupled to the means for controlling the power mode, wherein the means for detecting the clock stability is configured to:
determine stability of the second reference clock signal based on the first reference clock signal; and
provide a clock stability indication to the means for controlling the power mode if the second reference clock signal is determined stable;
wherein the means for controlling the power mode is configured to control the electronic circuit to switch from the first reference clock signal to the second reference clock signal in response to receiving the clock stability indication.

12 . A method for switching reference clocks in an electronic circuit, comprising:
switching from a lower-frequency reference clock to a higher-frequency reference clock, comprising:
determining stability of the higher-frequency reference clock based on the lower-frequency reference clock prior to switching to the higher-frequency reference clock; and
switching from the lower-frequency reference clock to the higher-frequency reference clock if the higher-frequency reference clock is determined stable.

13 . The method of claim 12 , further comprising switching from a low-power operation mode associated with the lower-frequency reference clock to a normal-power operation mode associated with the higher-frequency reference clock.

14 . The method of claim 12 , further comprising:
providing a clock stability detection request from a power control logic to enable an oscillation detection logic; receiving a clock stability indication from the oscillation detection logic if the higher-frequency reference clock is determined stable; providing an enable phase-locked loop (PLL) indication to a PLL control logic to control the PLL control logic to switch from the lower-frequency reference clock to the higher-frequency reference clock, wherein the enable PLL indication comprises a pll_en indicator that is set to one (1); and receiving a PLL locked indication from the PLL control logic when a PLL is phase locked with the higher-frequency reference clock, wherein the PLL locked indication comprises a pll_locked indicator that is set to 1.

15 . The method of claim 12 , further comprising switching from the higher-frequency reference clock to the lower-frequency reference clock.

16 . The method of claim 15 , further comprising switching from a normal-power operation mode associated with the higher-frequency reference clock to a low-power operation mode associated with the lower-frequency reference clock.

17 . The method of claim 15 , further comprising:
asserting a standard output status signal from a power control logic to prevent shutdown of the higher-frequency reference clock; providing a disable phase-locked loop (PLL) indication to a PLL control logic to control the PLL control logic to switch from the higher-frequen

Assignees

• Qualcomm Inc

Inventors

• Winemiller Chad Everett
• Amelifard Behnam
• Arcudia Kenneth Luis
• Boyette Jon Raymond
• Chang Chia Heng
• Deans Russell Coleman
• Spears Kevin Wayne

Classifications

• H03L7/0802 Primary

  the loop being adapted for reducing power consumption (H03L7/14 takes precedence) · CPC title

• G06F1/12 Primary

  Synchronisation of different clock signals {provided by a plurality of clock generators} · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title

• G06F1/04 Primary

  Generating or distributing clock signals or signals derived directly therefrom · CPC title

• G06F1/3237

  by disabling clock generation or distribution · CPC title