Low Power Asynchronous Counters in a Synchronous System

Patent metadata

Field	Value
Publication number	US-2016109901-A1
Application number	US-201514918406-A
Country	US
Kind code	A1
Filing date	Oct 20, 2015
Priority date	Oct 20, 2014
Publication date	Apr 21, 2016
Grant date	—

Abstract

A clock synchronizer adapted to synchronize reading a Timer that is clocked asynchronously to the system clock.

First claim

What is claimed is:

1 . An apparatus comprising:
an internal clock coupled to a synchronizer facility; an enable coupled to said synchronizer facility; a synchronous clock coupled to said synchronizer facility; said synchronizer facility coupled to a timer; said synchronizer facility being adapted to output a first synchronized clock as a function of said internal clock, said synchronous clock, and said enable; and said timer being adapted to count as a function of said first synchronized clock.

2 . The apparatus of claim 1 wherein said synchronizer facility is further characterized as comprising:
a first flip-flop adapted to:
receive said internal clock;
receive said synchronous clock;
receive said enable;
output a second synchronized clock as a function of said internal clock and said synchronous clock if said enable is de-asserted; and
output said second synchronized clock as a function of said internal clock and said enable if said enable is asserted;

a second flip-flop adapted to:
receive said second synchronized clock;
receive said synchronous clock;
receive said internal clock;
receive said enable;
output a third synchronized clock as a function of said second synchronized clock and said synchronous clock if said enable is de-asserted; and
output said third synchronized clock as a function of said internal clock and said enable if said enable is asserted; and

a first gating circuit adapted to output said first synchronized clock as a function of said third synchronized clock and said internal clock.

3 . The clock synchronization facility of claim 2 wherein said said internal clock is asynchronous to said synchronous clock.

4 . The clock synchronization facility of claim 3 where said enable is asynchronous to said internal clock.

5 . A method comprising:
receiving an internal clock; receiving an enable; receiving a synchronous clock; developing a first synchronized clock as a function of said internal clock, said synchronous clock, and said enable; and counting as a function of said first synchronized clock.

6 . The method of claim 5 wherein said developing step is further characterized as comprising the steps of:
selectively storing said internal clock as a function of:
said synchronous clock if said enable is de-asserted; and
said enable if said enable is asserted;

outputting a second synchronized clock as a function of said selectively stored internal clock;
selectively storing said second synchronized clock as a function of
said synchronous clock if said enable is de-asserted; and
said enable if said enable is asserted;

outputting a third synchronized clock as a function of said selectively stored second synchronized clock; and
developing said first synchronized clock as a function of said third synchronized clock and said internal clock;

7 . The method of claim 6 wherein said internal clock is asynchronous to said synchronous clock.

8 . The method of claim 7 wherein said enable is asynchronous to said internal clock.

9 . A clock synchronization facility configured to perform the steps of a method according to any one of claims 5 to 8 .

10 . An electronic system comprising a voltage converter facility according to claim 9 .

11 . A computer readable medium including executable instructions which, when executed in a processing system, causes the processing system to perform the steps of a method according to any one of claims 5 to 8 .

Assignees

• Ambiq Micro Inc

Inventors

• Sheafor Stephen James

Classifications

• H03L7/181

  a numerical count result being used for locking the loop, the counter counting during fixed time intervals {(H03L7/1806 takes precedence)} · CPC title

• G06F1/3287

  by switching off individual functional units in the computer system · CPC title

• H02M3/158

  including plural semiconductor devices as final control devices for a single load · CPC title

• G06F1/06 Primary

  Clock generators producing several clock signals {(G06F1/08 - G06F1/14 take precedence)} · CPC title

• G06F13/102

  where the program performs an interfacing function, e.g. device driver (G06F13/105 takes precedence; contention policies within device drivers G06F9/4881; scheduling within device drivers G06F9/52) · CPC title