Full nanosheet airgap spacer

Patent metadata

Field	Value
Publication number	US-11894442-B2
Application number	US-202117358275-A
Country	US
Kind code	B2
Filing date	Jun 25, 2021
Priority date	Jun 25, 2021
Publication date	Feb 6, 2024
Grant date	Feb 6, 2024

Abstract

Embodiments disclosed herein include a nanosheet transistor for reducing parasitic capacitance. The nanosheet transistor may include a spacer region between a high-k metal gate and an epitaxial layer. The spacer region may include a first nanosheet stack with a first nanosheet and a second nanosheet. The spacer region may include an inner spacer region between the first nanosheet and the second nanosheet, and a side subway region located along an edge of the first nanosheet, the inner spacer region, and the second nanosheet.

First claim

What is claimed is:

1. A nanosheet transistor for reducing parasitic capacitance, comprising:
a spacer region between a high-k metal gate and an epitaxial layer, wherein the spacer region comprises:
a first nanosheet stack comprising a first nanosheet and a second nanosheet;
an inner spacer region between the first nanosheet and the second nanosheet; and
a side subway region located along an edge of the first nanosheet, the inner spacer region, and the second nanosheet, wherein the side subway region contacts a shallow trench isolation below the spacer region.

2. The nanosheet transistor of claim 1 , wherein the inner spacer region consists of an air gap.

3. The nanosheet transistor of claim 2 , further comprising a non-formal dielectric deposition closing off the air gap.

4. The nanosheet transistor of claim 1 , wherein the spacer region comprises a dielectric above the first nanosheet.

5. The nanosheet transistor of claim 1 , wherein the spacer region comprises:
a second nanosheet stack between the high-k metal gate and the epitaxial layer; and
a spacer dielectric between the first nanosheet stack and the second nanosheet stack.

6. The nanosheet transistor of claim 5 , wherein the side subway region is located between the first stack and the spacer dielectric.

7. The nanosheet transistor of claim 1 , wherein the side subway region comprises an air gap.

8. A method of fabricating a nanosheet transistor, comprising:
forming a nanosheet stack comprising sacrificial inner spacers and nanosheets;
forming an epitaxial layer adjacent to the nanosheet stack;
indenting the epitaxial layer to expose the sacrificial inner spacer at a corner etch; and
removing the sacrificial inner spacer to form an air gap around the nanosheets.

9. The method of claim 8 , comprising:
cutting a contact cut through an interlayer dielectric layer; and
etching a spacer within the contact cut to expose the epitaxial layer.

10. The method of claim 8 , comprising forming a spacer between the nanosheet stack and a substrate.

11. The method of claim 8 , wherein the air gap comprises a side subway region along an edge of the nanosheets.

12. The method of claim 8 , comprising filling the corner etch with a non-formal dielectric deposition.

13. The method of claim 12 , comprising forming a trench contact around the non-formal dielectric deposition.

14. The method of claim 8 , wherein removing the sacrificial inner spacer comprises etching the sacrificial inner spacer through the corner etch.

15. A nanosheet transistor for reducing parasitic capacitance, comprising:
a spacer region between a high-k metal gate and an epitaxial layer, wherein the spacer region comprises:
a first nanosheet stack comprising a first nanosheet and a second nanosheet;
an inner spacer region between the first nanosheet and the second nanosheet, wherein the inner spacer region comprises an air gap over a width of the first nanosheet and the second nanosheet, wherein the air gap contacts a shallow trench isolation below the first nanosheet stack.

16. The nanosheet transistor of claim 15 , wherein the spacer region comprises a side subway region located along an edge of the first nanosheet, the inner spacer region, and the second nanosheet.

17. The nanosheet transistor of claim 16 , wherein the side subway region comprises a side subway region air gap.

18. The nanosheet transistor of claim 15 , further comprising a non-formal dielectric deposition closing off the air gap.

19. The nanosheet transistor of claim 15 , wherein the spacer region comprises:
a second nanosheet stack between the high-k metal gate and the epitaxial layer; and
a spacer dielectric between the first nanosheet stack and the second nanosheet stack.

20. The nanosheet transistor of claim 19 , comprising a side subway region located between the first stack and the spacer dielectric.

Assignees

• IBM

Inventors

• Zhang Jingyun
• Xie Ruilong
• Vega Reinaldo
• Cheng Kangguo
• Yu Lan

Classifications

• H10D62/118

  Nanostructure semiconductor bodies · CPC title

• H10D30/6735

  having gates fully surrounding the channels, e.g. gate-all-around · CPC title

• H10D64/018

  Spacers formed inside holes at the prospective gate locations, e.g. holes left by removing dummy gates · CPC title

• H10D64/017

  using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes · CPC title

• H10D62/116

  adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions · CPC title