Gate spacer and inner spacer formation for nanosheet transistors having relatively small space between adjacent gates

Patent metadata

Field	Value
Publication number	US-10971585-B2
Application number	US-201815969855-A
Country	US
Kind code	B2
Filing date	May 3, 2018
Priority date	May 3, 2018
Publication date	Apr 6, 2021
Grant date	Apr 6, 2021

Abstract

Embodiments of the invention are directed to a nano sheet semiconductor device fabrication method that includes forming a gate spacer along a gate region of the nanosheet FET device. Channel nanosheet is formed such that each one has a desired final channel nanosheet width dimension (Wf). An inner spacer is formed between the channel nanosheets. Forming the gate spacer and the inner spacer includes, subsequent to forming the channel nanosheets to the desired Wf, conformally depositing a layer of the spacer material along a sidewall of the gate region, along sidewalls of the channel nanosheets, and within a space between the channel nanosheets. The gate spacer is formed from a portion of the layer of the spacer material along the sidewall of the gate region. The inner spacer is formed from a portion of the layer of the spacer material within the space between the channel nanosheets.

First claim

What is claimed is:

1. A method of fabricating a semiconductor device, the method comprising:
performing fabrication operations to form a nanosheet field effect transistor (FET) device on a substrate;
wherein the fabrication operations include:
forming a gate spacer along a gate region of the nanosheet FET device;
forming channel nanosheets to a desired final channel nanosheet width dimension (Wf) for each of the channel nanosheets;
forming an inner spacer between the channel nanosheets;
wherein the gate spacer and the inner spacer comprise the same type of spacer material;
wherein forming the gate spacer and the inner spacer comprises, subsequent to forming the channel nanosheets to the desired Wf, conformally depositing a layer of the spacer material having a first thickness dimension to extend along a sidewall of the gate region, sidewalls of the channel nanosheets, and within a space between the channel nanosheets;
wherein forming the gate spacer and the inner spacer further comprises performing an etch operation that removes a portion of the layer of spacer material that extends along sidewalls of the channel nanosheets; and
separately from forming the gate spacer and the inner spacer by performing the etch operation that removes the portion of the layer of spacer material that extends along sidewalls of the channel nanosheets, trimming a portion of the layer of the spacer material that is along the sidewall of the gate region such that the portion of the spacer layer that is along the sidewall of the gate region comprises a second thickness dimension that is less than the first thickness dimension;
wherein the gate spacer comprises the portion of the layer of the spacer material that comprises the second thickness dimension and is along the sidewall of the gate region;
wherein the inner spacer comprises a portion of the layer of the spacer material that is within the space between the channel nanosheets.

2. The method of claim 1 , wherein the gate spacer comprises a gate spacer sidewall.

3. The method of claim 2 , wherein the inner spacer comprises an inner spacer sidewall.

4. The method of claim 3 , wherein the gate spacer sidewall is substantially co-planar with the inner spacer sidewall.

5. The method of claim 1 , wherein the spacer material comprises a low-k material.

6. The method of claim 1 , wherein forming the channel nanosheets to the desired Wf comprises forming dummy gate spacers over channel nanosheet layers.

7. The method of claim 6 , wherein forming the channel nanosheets to the desired Wf further comprises removing portions of the channel nanosheet layers that are not covered by the dummy gates spacers.

8. The method of claim 7 , wherein the fabrication operations further comprise removing the dummy gate spacers prior to conformally depositing the layer of the spacer material to extend along the sidewall of the gate region, the sidewalls of the channel nanosheets, and within the space between the channel nanosheets.

9. A method of fabricating adjacent semiconductor devices, the method comprising:
performing fabrication operations to form a first nanosheet field effect transistor (FET) device and a second nanosheet FET on a substrate;
wherein the fabrication operations to form the first nanosheet FET include:
forming a first gate spacer along a first gate region of the first nanosheet FET device;
forming first channel nanosheets to a desired first final channel nanosheet width dimension (F-Wf) for each of the first channel nanosheets; and
forming a first inner spacer between the first channel nanosheets;

wherein the fabrication operations to form the second nanosheet FET include:
forming a second gate spacer along a second gate region of the second nanosheet FET device;
forming second channel nanosheets to a desired second final channel nanosheet width dimension (S-Wf) for each of the second channel nanosheets;
forming a second inner spacer between the second channel nanosheets;
wherein the first gate spacer, the second gate spacer, the first inner spacer, and the second inner spacer comprise the same type of spacer material;
wherein F-Wf is substantially the same as S-Wf;
wherein forming the first gate spacer, the second gate spacer, the first inner spacer, and the second inner spacer comprises, subsequent to forming the first channel nanosheets to the F-Wf and forming the second channel nanosheets to the S-Wf, conformally depositing a layer of the spacer material having a first thickness dimension to extend along a sidewall of the first gate region, a sidewall of the second gate region, sidewalls of the first channel nanosheets, sidewalls of the second channel nanosheets, within a space between the first channel nanosheets, and within a space between the second channel nanosheets;
separately from forming the layer of the spacer material having the first thickness, trimming a portion of the layer of the spacer material that is along the sidewall of the first gate region such that the portion of the spacer layer that is along the sidewall of the first gate region comprises a second thickness dimension that is less than the first thickness dimension;
wherein forming the first gate spacer, the second gate spacer, the first inner spacer, and the second inner spacer further comprises performing an etch operation that removes a portion of the layer of spacer material that extends along sidewalls of the first channel nanosheets and along sidewalls of the second channel nanosheets; and
separately from forming the first gate spacer, the second gate spacer, the first inner spacer, and the second inner spacer by performing an etch operation that removes a portion of the layer of spacer material that extends along sidewalls of the first channel nanosheets and along sidewalls of the second channel nanosheets, trimming a portion of the layer of the spacer material that is along the sidewall of the second gate region such that the portion of the spacer layer that is along the sidewall of the second gate region comprises the second thickness dimension that is less than the first thickness dimension;
wherein a trimmed first gate spacer comprises the portion of the layer of the spacer material that comprises the second thickness dimension and is along the sidewall of the first gate region;
wherein the first inner spacer comprises a portion of the layer of the spacer material that is within the space between the first channel nanosheets;
wherein a trimmed second gate spacer comprises the portion of the layer of the spacer material that comprises the second thickness dimension and is along the sidewall of the second gate region;
wherein the second inner spacer comprises a portion of the layer of the spacer material that is within the space between the second channel nanosheets.

10. The method of claim 9 , wherein a gate pitch from the first gate region to the second gate region is equal to or less than about 44 nanometers (nm).

11. The method of claim 9 , wherein:
the first gate spacer comprises a first gate spacer sidewall; and
the second gate spacer comprises a second gate spacer sidewall.

12. The method of claim 11 , wherein:
the first inner spacer comprises a first inner spacer sidewall; and
the second inner spacer comprises a second inner spacer sidewall.

13. The method of claim 12 , wherein:
the first gate spacer sidewall is substantially co-planar with the first inner spacer sidewall; and
the second gate spacer sidewall is substantially co-planar with the second inner spacer sidewall.

14. The method of claim 9 , wherein the spacer material comprises a low-k material.

Assignees

• IBM

Inventors

• Lee Choonghyun
• Ok Injo
• Seo Soon-Cheon
• Xu Wenyu

Classifications

• H10P50/642

  Chemical etching · CPC title

• H10P14/3462

  Nanowires · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10W10/011

  of isolation regions comprising dielectric materials · CPC title

• H10W10/10

  Isolation regions comprising dielectric materials · CPC title