Semiconductor memory device having a channel plug

Patent metadata

Field	Value
Publication number	US-11894360-B2
Application number	US-202117406987-A
Country	US
Kind code	B2
Filing date	Aug 19, 2021
Priority date	Apr 14, 2021
Publication date	Feb 6, 2024
Grant date	Feb 6, 2024

Abstract

A semiconductor device includes a slit pattern and a trench pattern disposed to extend substantially in parallel with each other in a first direction and channel plugs between the slit pattern and the trench pattern. The channel plugs include a first channel plug adjacent to the slit pattern. A top surface shape of the first channel plug is an elliptical shape. A long axis direction of the first channel plug and the first direction form an acute angle.

First claim

What is claimed is:

1. A semiconductor device comprising:
a slit pattern and a trench pattern disposed to extend substantially in parallel with each other in a first direction; and
channel plugs between the slit pattern and the trench pattern,
wherein:
the channel plugs comprise:
a first channel plug adjacent to the slit pattern,
a second channel plug between the first channel plug and the trench pattern;
a third channel plug between the second channel plug and the trench pattern;
a fourth channel plug between the third channel plug and the trench pattern; and
a fifth channel plug traversed by the trench pattern,
wherein:
a top surface shape of the first channel plug is an elliptical shape,
a top surface shape of each of the third channel plug and the fourth channel plug is substantially a circle shape,
a top surface shape of the fifth channel plug is substantially a separated circle shape separated by the trench pattern, and
a long axis direction of the first channel plug and the first direction form an acute angle.

2. The semiconductor device of claim 1 , wherein the trench pattern extends in a wave form in the first direction.

3. The semiconductor device of claim 1 , wherein a first distance between the slit pattern and the first channel plug is greater than a second distance between the first channel plug and the second channel plug.

4. The semiconductor device of claim 3 , wherein the second distance is greater than a third distance between the second channel plug and the third channel plug.

5. The semiconductor device of claim 4 , wherein the third distance is greater than a fourth distance between the third channel plug and the fourth channel plug.

6. The semiconductor device of claim 5 , wherein the fourth distance is greater than a fifth distance between the fourth channel plug and the trench pattern.

7. The semiconductor device of claim 1 , wherein a top surface shape or a cross-sectional shape of the second channel plug is substantially a circle shape.

8. The semiconductor device of claim 7 , wherein:
a diameter of the first channel plug in the long axis direction is greater than a diameter of the second channel plug, and
a diameter of the first channel plug in a short axis direction is substantially same as the diameter of the second channel plug.

9. The semiconductor device of claim 7 , wherein diameters of the second channel plug, the third channel plug, and the fourth channel plug are substantially the same as each other.

10. The semiconductor device of claim 1 , wherein a top surface shape of the second channel plug is substantially an elliptical shape.

11. The semiconductor device of claim 10 , wherein the long axis direction of the first channel plug and a long axis direction of the second channel plug are substantially in parallel with each other.

12. The semiconductor device of claim 10 , wherein the long axis direction of the first channel plug and a long axis direction of the second channel plug form an acute angle between 1° and 45°.

13. A semiconductor device comprising:
a slit pattern and a trench pattern extending substantially in parallel with each other in a first direction; and
channel plugs between the slit pattern and the trench pattern,
wherein the channel plugs comprise:
a first channel plug adjacent to the slit pattern, the first channel plug having an elliptical top surface shape or an elliptical cross-sectional shape;
a second channel plug between the first channel plug and the trench pattern;
a third channel plug between the second channel plug and the trench pattern; and
a fourth channel plug between the third channel plug and the trench pattern,
wherein a first distance between the slit pattern and the first channel plug is greater than a second distance between the first channel plug and the second channel plug.

14. The semiconductor device of claim 13 , wherein a long axis direction of the first channel plug and the first direction form an acute angle between 1° and 45°.

15. The semiconductor device of claim 13 , wherein:
the second distance is greater than a third distance between the second channel plug and the third channel plug, and
the third distance is greater than a fourth distance between the third channel plug and the fourth channel plug.

16. The semiconductor device of claim 13 , further comprising:
a fifth channel plug being traversed by the trench pattern.

17. The semiconductor device of claim 13 , wherein the trench pattern extends in a wave form in the first direction.

18. A semiconductor device comprising:
two slit patterns extending substantially in parallel with each other in a first direction;
a trench pattern between the two slit patterns extending in parallel with the slit patterns in the first direction; and
channel plugs between the slit patterns and the trench pattern,
wherein the slit patterns, the trench pattern, and the channel plugs are disposed in a cell region,
wherein the channel plugs comprise:
two first channel plugs adjacent to the slit patterns, respectively;
two second channel plugs between the two first channel plugs;
two third channel plugs between the two second channel plugs; and
two fourth channel plugs between the two third channel plugs, wherein:
the two first, second, third, and fourth channel plugs are arranged in a zigzag form in a second direction perpendicular to the first direction,
the trench pattern is disposed between the two fourth channel plugs,
top surface shapes of the two first channel plugs are an elliptical shape,
a maximum diameter of each of the two first channel plugs are greater than a maximum diameter of each of the two second, third, and the fourth channel plugs,
a long axis direction of the first two channel plugs and the first direction form an acute angle greater than 1° and less than 90°.

19. The semiconductor device of claim 18 ,
wherein:
each of the two first channel plugs is partially overlapped with the each of the two second channel plugs in the first direction,
each of the two second channel plugs is partially overlapped with the each of the two third channel plugs in the first direction, and
each of the two third channel plugs is partially overlapped with the each of the two fourth channel plugs in the first direction.

20. The semiconductor device of claim 18 ,
wherein:
each of the two first channel plugs is partially overlapped with the each of the two second channel plugs in the second direction,
each of the two second channel plugs is partially overlapped with the each of the two third channel plugs in the second direction, and
each of the two third channel plugs is partially overlapped with the each of the two fourth channel plugs in the second direction.

Assignees

• Sk Hynix Inc

Inventors

• Kim Jang Won

Classifications

• H10W20/40

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title

• H10D62/292

  Non-planar channels of IGFETs (resulting from the gate electrode dispositions, e.g. within trenches H10D64/512) · CPC title

• H10D89/10 Primary

  Integrated device layouts · CPC title

• H10B43/10 Primary

  characterised by the top-view layout · CPC title

• H01L27/0207 Primary

  Electricity · mapped topic