Semiconductor fabrication method and structure using multiple sacrificial layers to form sidewall spacers

Patent metadata

Field	Value
Publication number	US-11894231-B2
Application number	US-202117208511-A
Country	US
Kind code	B2
Filing date	Mar 22, 2021
Priority date	Apr 8, 2020
Publication date	Feb 6, 2024
Grant date	Feb 6, 2024

Abstract

Semiconductor structures and fabrication methods thereof are provided. The method may include providing a to-be-etched layer; forming a plurality of core layers on the to-be-etched layer, wherein a first opening and a second opening are formed between different adjacent core layers and a width of the first opening is smaller than a width of the second opening; forming a first sacrificial material layer on the to-be-etched layer and the plurality of core layers; forming a second sacrificial layer on a portion of the first sacrificial material layer in the first opening to form a sacrificial structure in the first opening; removing the plurality of core layers after forming the sacrificial structure; forming sidewall spacers on sidewall surfaces of the sacrificial structure after removing the plurality of core layers; and removing the sacrificial structure after forming the sidewall spacers.

First claim

What is claimed is:

1. A method for forming a semiconductor structure, comprising:
providing a to-be-etched layer;
forming a plurality of core layers on the to-be-etched layer, wherein a first opening and a second opening are formed between different adjacent core layers, and a width of the first opening is smaller than a width of the second opening;
forming a first sacrificial material layer on the to-be-etched layer and the plurality of core layers, the first sacrificial material layer being formed on a top surface and sidewall surfaces of the first opening and the second opening and on top surfaces of the plurality of core layers;
forming an initial second sacrificial layer on a top surface and sidewall surfaces of the first sacrificial material layer in the first opening to fully fill the first opening and on sidewall surfaces of the first sacrificial material layer in the second opening, the initial second sacrificial layer being formed after the first sacrificial material layer is formed without removing a portion of the first sacrificial material layer;
after the initial second sacrificial layer is formed, removing a portion of the initial second sacrificial layer on the sidewall surfaces of the first sacrificial material layer in the second opening to form a second sacrificial layer on the top surface and the sidewall surfaces of the first sacrificial material layer in the first opening only and fully filing the first opening;
after forming the second sacrificial layer, removing a portion of the first sacrificial material layer on the top surfaces of the plurality of core layers to form an initial first sacrificial layer;
removing the plurality of core layers after forming the initial first sacrificial layer and the second sacrificial layer;
modifying the initial first sacrificial layer to form a first sacrificial layer;
forming sidewall spacers on sidewall surfaces of the first sacrificial layer after removing the plurality of core layers;
after forming the sidewall spacers, removing the second sacrificial layer;
after removing the second sacrificial layer, removing the first sacrificial layer, a material of the second sacrificial layer being different from a material of the first sacrificial layer; and
after removing the first sacrificial layer, forming a semiconductor structure by etching the to-be etched layer using the sidewall spacers as a mask.

2. The method according to claim 1 , wherein forming the initial second sacrificial layer comprises:
forming the initial second sacrificial layer on the first sacrificial material layer, the initial second sacrificial layer being formed on the top surface and the sidewall surfaces of the first sacrificial material layer in the first opening to fully fill the first opening, on a top surface and the sidewall surfaces of the first sacrificial material layer in the second opening, and on the first sacrificial material layer on the top surfaces of the plurality of core layers; and
etching back the initial second sacrificial layer until a surface of the first sacrificial material layer is exposed.

3. The method according to claim 1 , wherein:
the material of the second sacrificial layer includes an inorganic material; and
the inorganic material includes silicon oxide.

4. The method according to claim 1 , wherein forming the initial first sacrificial layer comprises:
etching back the first sacrificial material layer after forming the second sacrificial layer until a surface of the to-be-etched layer is exposed to form the initial first sacrificial layer on inner sidewall surfaces of the plurality of core layers.

5. The method according to claim 4 , wherein:
the material of the first sacrificial layer is different from a material of the sidewall spacers.

6. The method according to claim 5 , wherein:
the material of the first sacrificial layer includes a metal-containing material;
the metal-containing material includes one or more of titanium oxide and aluminum oxide; the material of the sidewall spacers includes an amorphous material; and
the amorphous material includes amorphous silicon.

7. The method according to claim 5 , wherein:
the material of the sidewall spacers includes a metal-containing material;
the metal-containing material includes one or more of titanium oxide and aluminum oxide;
the material of the first sacrificial layer includes an amorphous material; and
the amorphous material includes amorphous silicon.

8. The method according to claim 1 , wherein:
modifying the initial first sacrificial layer includes an ion implantation process; and
ions of the ion implantation process include carbon ions, nitrogen ions, boron ions, or fluoride ions.

9. The method according to claim 8 , wherein:
the material of the first sacrificial layer is same as a material of the sidewall spacers.

10. The method according to claim 9 , wherein:
the material of the first sacrificial layer includes an amorphous material;
the amorphous material includes amorphous silicon;
the material of the sidewall spacers includes an amorphous material; and
the amorphous material includes amorphous silicon.

11. The method according to claim 5 , wherein:
the material of the first sacrificial layer is different from a material of the plurality of core layers; and
the material of the second sacrificial layer is different from the material of the plurality of core layers.

12. The method according to claim 11 , wherein:
the material of the plurality of core layers includes an inorganic material; and
the inorganic material includes silicon nitride.

13. The method according to claim 1 , wherein:
the to-be-etched layer includes a substrate and a transition structure on the substrate.

14. The method according to claim 13 , wherein:
a material of the transition structure is different from the material of the first sacrificial layer;
the material of the transition structure is different from a material of the sidewall spacers; and
the material of the transition structure includes an inorganic material, and the inorganic material includes silicon oxide.

Assignees

• Semiconductor Mfg Int Shanghai Corp
• Semiconductor Mfg Int Beijing Corp

Inventors

• Zhang Haiyang
• Tang Longjuan
• Yang Chenxi

Classifications

• H10P76/4085 Primary

  characterised by the processes involved to create the masks · CPC title

• H10P76/4083

  characterised by their behaviours during the lithography processes, e.g. soluble masks or redeposited masks · CPC title

• H10P76/405

  characterised by their composition, e.g. multilayer masks · CPC title

• H10P76/4088 Primary

  Processes for improving the resolution of the masks · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title