Memory system including a nonvolatile memory device, and an erasing method thereof

Patent metadata

Field	Value
Publication number	US-11894092-B2
Application number	US-202117325690-A
Country	US
Kind code	B2
Filing date	May 20, 2021
Priority date	Aug 10, 2020
Publication date	Feb 6, 2024
Grant date	Feb 6, 2024

Abstract

A fail detecting method of a memory system including a nonvolatile memory device and a memory controller, the fail detecting method including: counting, by the memory controller, the number of erases of a word line connected to a pass transistor; issuing a first erase command, by the memory controller, when the number of erases reaches a reference value; applying a first voltage, by the nonvolatile memory device, in response to the first erase command, that causes a gate-source potential difference of the pass transistor to have a first value; detecting, by the memory controller, a leakage current in a word line, after the applying of the first voltage; and determining, by the memory controller, the word line as a fail when a leakage voltage caused by the leakage current is greater than a first threshold value.

First claim

What is claimed is:

1. A fail detecting method of a memory system comprising a nonvolatile memory device and a memory controller, the fail detecting method comprising:
counting, by the memory controller, the number of erases of a word line connected to a pass transistor;
issuing a first erase command, by the memory controller, when the number of erases reaches a reference value;
applying a first voltage, by the nonvolatile memory device, in response to the first erase command, that causes a gate-source potential difference of the pass transistor to have a first value;
detecting, by the memory controller, a leakage current in the word line, after the applying of the first voltage; and
determining, by the memory controller, the word line as a fail when a leakage voltage caused by the leakage current is greater than a first threshold value.

2. The fail detecting method of claim 1 , wherein the applying of the first voltage comprises increasing a source terminal voltage of the pass transistor.

3. The fail detecting method of claim 1 , wherein the applying of the first voltage comprises decreasing a gate terminal voltage of the pass transistor.

4. The fail detecting method of claim 1 , further comprising:
applying a second voltage, by the nonvolatile memory device, that causes the gate-source potential difference to have a second value greater than the first value; and
performing an erase operation, by the nonvolatile memory device, on a memory block connected to the word line.

5. The fail detecting method of claim 1 , wherein the determining of the word line as a fail comprises:
determining that the pass transistor is turned off; and
identifying a word line, connected to the pass transistor that is turned off, as a fail word line.

6. The fail detecting method of claim 1 , further comprising:
applying a dummy voltage to a memory cell connected to the word line, after the number of erases reaches the reference value; and
buffering a program voltage.

7. The fail detecting method of claim 1 , wherein the detecting of the leakage current comprises determining that a difference between the gate-source potential difference and a threshold voltage of the pass transistor is less than or equal to the leakage voltage.

8. The fail detecting method of claim 1 , wherein the first threshold value is an overdrive voltage.

9. An erase method of a nonvolatile memory device, the erase method comprising:
receiving an erase command;
applying a first voltage, in a first erase mode based on the erase command, that causes a gate-source potential difference of a pass transistor connected to a word line to have a first value;
detecting a leakage current on the word line when the pass transistor is off;
identifying the word line, connected to the pass transistor that is turned off, as a fail word line; and
in a second erase mode, erasing a memory block connected to the word line as a second voltage is applied that causes the gate-source potential difference to have a second value greater than the first value.

10. The erase method of claim 9 , wherein the applying of the first voltage further comprises increasing a source terminal voltage of the pass transistor.

11. The erase method of claim 9 , wherein the applying of the first voltage further comprises decreasing a gate terminal voltage of the pass transistor.

12. The erase method of claim 9 , wherein the first erase mode and the second erase mode are entered by the erase command.

13. The erase method of claim 9 , wherein the detecting of the leakage current comprises maintaining an erase voltage applied to a memory cell at a first voltage level, and
the erasing of the memory block comprises maintaining the erase voltage at a second voltage level different from the first voltage level.

14. The erase method of claim 9 , wherein the detecting of the leakage current further comprises confirming that a source voltage of the pass transistor is higher than a first verify voltage level.

15. The erase method of claim 9 , wherein the detecting of the leakage current comprises:
determining that the pass transistor is turned off.

16. The erase method of claim 9 , further comprising counting the number of erases of the word line,
wherein the first erase mode is entered when the number of erases reaches a predetermined value.

17. The erase method of claim 16 , further comprising:
applying a dummy voltage to the memory block, when the numbers of erases reaches the predetermined value; and
buffering a program voltage.

18. A memory system comprising:
a nonvolatile memory device; and
a memory controller configured to control the nonvolatile memory device,
wherein the nonvolatile memory device comprises:
a memory cell region comprising a first metal pad;
a peripheral region comprising a second metal pad, the peripheral region being connected to the memory cell region through the first metal pad and the second metal pad;
a memory cell array comprising a plurality of memory cells forming a plurality of strings in a direction substantially perpendicular to a substrate, the memory cell array being included in the memory cell region;
wherein the peripheral region further comprises:
a row decoder comprising a pass transistor configured to switch a plurality of word lines connected to the plurality of memory cells, configured to select, through the plurality of word lines, a memory block that is included in the memory cell array;
a voltage generator included in the peripheral region and configured to generate a plurality of voltages provided to the memory cell array and the pass transistor; and
a control logic included in the peripheral region and configured to decrease, based on a first erase command, a gate-source potential difference of the pass transistor to detect a leakage current of a word line in the memory block,
wherein the memory controller is configured to count the number of erases of the memory block, issue the first erase command when the number of erases reaches a reference value, and detect the leakage current.

19. The memory system of claim 18 , wherein the voltage generator increases a voltage applied to a source terminal of the pass transistor.

20. The memory system of claim 18 , wherein the voltage generator decreases a voltage applied to a gate terminal of the pass transistor.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Son Myoungho
• Jung Wontaeck
• Nam Buil

Classifications

• H10W90/792

  between multiple chips · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W80/00

  Direct bonding of chips, wafers or substrates · CPC title

• H10W72/944

  Dispositions of multiple bond pads · CPC title

• H10W72/926

  Multiple bond pads having different sizes · CPC title