Sense amplifier, memory and method for controlling sense amplifier

Patent metadata

Field	Value
Publication number	US-11894047-B2
Application number	US-202017441780-A
Country	US
Kind code	B2
Filing date	Dec 25, 2020
Priority date	Jul 27, 2020
Publication date	Feb 6, 2024
Grant date	Feb 6, 2024

Abstract

The present disclosure provides a sense amplifier, a memory, and a method for controlling a sense amplifier, relating to the technical field of semiconductor memories. The sense amplifier comprises: an amplification module; and an offset voltage storage unit electrically connected to the amplification module; wherein, in an offset cancellation stage of the sense amplifier, the sense amplifier is configured to comprise a current mirror structure to store an offset voltage of the amplification module in an offset voltage storage unit. The present disclosure can realize the offset cancellation of the sense amplifier.

First claim

The invention claimed is:

1. A sense amplifier, comprising:
an amplification module; and
an offset voltage storage unit, electrically connected to the amplification module;
wherein the amplification module comprises:
a first p-channel metal-oxide semiconductor (PMOS) transistor;
a second PMOS transistor, a source of the second PMOS transistor being connected to a source of the first PMOS transistor;
a first n-channel metal-oxide semiconductor (NMOS) transistor, a drain of the first NMOS transistor being connected to a drain of the first PMOS transistor and a first terminal of the offset voltage storage unit, and a gate of the first NMOS transistor being connected to a gate of the first PMOS transistor; and
a second NMOS transistor, a drain of the second NMOS transistor being connected to a drain of the second PMOS transistor, a source of the second NMOS transistor being connected to a source of the first NMOS transistor, and a gate of the second NMOS transistor being connected to a second terminal of the offset voltage storage unit;

wherein, in an offset cancellation stage of the sense amplifier, the first PMOS transistor and the second PMOS transistor are configured as a current mirror, and the first NMOS transistor and the second NMOS transistor are both configured by using a diode connection mode, to store an offset voltage of the amplification module in the offset voltage storage unit.

2. The sense amplifier according to claim 1 , wherein the drain of the first PMOS transistor is connected to the drain of the first NMOS transistor at a first node, and the drain of the second PMOS transistor is connected to the drain of the second NMOS transistor at a second node; the sense amplifier further comprises:
a first switch, a first terminal of the first switch being connected to the first node, and a second terminal of the first switch being connected to the gate of the first NMOS transistor;
a second switch, a first terminal of the second switch being connected to the second node, and a second terminal of the second switch being connected to the gate of the second NMOS transistor; and
a third switch, a first terminal of the third switch being connected to the gate of the first PMOS transistor, and a second terminal of the third switch being connected to a gate of the second PMOS transistor;
wherein, in the offset cancellation stage of the sense amplifier, the first switch, the second switch and the third switch are all in a closed state.

3. The sense amplifier according to claim 2 , wherein the sense amplifier further comprises:
a pull-up unit, configured to control a connection state between the source of the first PMOS transistor and a power supply voltage in response to a pull-up control signal; and
a pull-down unit, configured to control the source of the first NMOS transistor to be connected to a ground or disconnected from the ground in response to a pull-down control signal;
wherein, in the offset cancellation stage of the sense amplifier, the source of the first PMOS transistor is connected to the power supply voltage, and the source of the first NMOS transistor is connected to the ground.

4. The sense amplifier according to claim 2 , wherein the first switch further comprises a control terminal configured to control an on-off state of the first switch in response to a first control signal;
the second switch further comprises a control terminal configured to control an on-off state of the second switch in response to a second control signal; and
the third switch further comprises a control terminal configured to control an on-off state of the third switch in response to the second control signal.

5. The sense amplifier according to claim 3 , wherein the sense amplifier further comprises:
a fourth switch, a first terminal of the fourth switch being connected to the gate of the first NMOS transistor, and a second terminal of the fourth switch being connected to the second node; and
a fifth switch, a first terminal of the fifth switch being connected to the gate of the second PMOS transistor, and a second terminal of the fifth switch being connected to the gate of the second NMOS transistor;
wherein, in the offset cancellation stage of the sense amplifier, the fourth switch and the fifth switch are both open.

6. The sense amplifier according to claim 5 , wherein the fourth switch further comprises a control terminal configured to control an on-off state of the fourth switch in response to a third control signal; and
the fifth switch further comprises a control terminal configured to control an on-off state of the fifth switch in response to the third control signal.

7. The sense amplifier according to claim 6 , wherein the sense amplifier further comprises:
a sixth switch, a first terminal of the sixth switch being connected to a first bit line, and a second terminal of the sixth switch being connected to the first node; and
a seventh switch, a first terminal of the seventh switch being connected to a second bit line, and a second terminal of the seventh switch being connected to the second node;
wherein, in the offset cancellation stage of the sense amplifier, the sixth switch and the seventh switch are both open.

8. The sense amplifier according to claim 7 , wherein the sixth switch further comprises a control terminal configured to control an on-off state of the sixth switch in response to a fourth control signal; and
the seventh switch further comprises a control terminal configured to control an on-off state of the seventh switch in response to the fourth control signal.

9. The sense amplifier according to claim 8 , wherein, after the offset cancellation stage of the sense amplifier, a storage unit corresponding to the first bit line or a storage unit corresponding to the second bit line is turned on, the first switch is open, the second switch and the third switch are open, the source of the first PMOS transistor is disconnected from the power supply voltage, the source of the first NMOS transistor is disconnected from the ground, the fourth switch and the fifth switch are closed, and the sixth switch and the seventh switch are closed to input a voltage difference between the first bit line and the second bit line into the sense amplifier.

10. The sense amplifier according to claim 9 , wherein, in a case where the voltage difference between the first bit line and the second bit line is input to the sense amplifier, the source of the first PMOS transistor is connected to the power supply voltage, and the source of the first NMOS transistor is connected to the ground, to amplify the voltage difference.

11. The sense amplifier according to claim 7 , wherein the sense amplifier further comprises:
a pre-charge unit, configured to pre-charge the first bit line and the second bit line when the sense amplifier is in a pre-charge stage.

12. The sense amplifier according to claim 11 , wherein the pre-charge stage and the offset cancellation stage are configured to be executed simultaneously.

13. A memory, comprising the sense amplifier according to claim 1 .

14. A method for controlling a sense amplifier, wherein the sense amplifier comprises an amplification module and an offset voltage storage unit;
wherein the amplification module comprises:
a first p-channel metal-oxide semiconductor (PMOS) transistor;
a second PMOS transistor, a source of the second PMOS transistor being connected to a source of the first PMOS transistor;
a first n-channel metal-oxide semiconductor (NMOS) transistor, a drain of the first NMOS transistor being connected to a drain of the first PMOS transistor and a first terminal o

Assignees

• Univ Anhui
• Changxin Memory Tech Inc

Inventors

• Peng Chunyu
• Zhao Yangkuo
• Lu Wenjuan
• Wu Xiulong
• Lin Zhiting
• Chen Junning
• Li Xin
• Ji Rumin
• He Jun
• Ying Zhan

Classifications

• G11C11/4091 Primary

  Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating · CPC title

• G11C7/08 Primary

  Control thereof · CPC title

• G11C7/065 Primary

  Differential amplifiers of latching type · CPC title

• G11C7/06

  Sense amplifiers; Associated circuits {, e.g. timing or triggering circuits} · CPC title

• G11C7/12

  Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines · CPC title