Offset cancellation for latching in a memory device

Patent metadata

Field	Value
Publication number	US-11087817-B2
Application number	US-202016866204-A
Country	US
Kind code	B2
Filing date	May 4, 2020
Priority date	Jul 20, 2017
Publication date	Aug 10, 2021
Grant date	Aug 10, 2021

Abstract

Methods, systems, and devices for offset cancellation for latching in memory devices are described. A memory device may include a sense component comprising a first and second transistor. In some cases, a memory device may further include a first capacitor coupled to the first transistor and a second capacitor coupled to the second transistor and a first switching component coupled between a voltage source and the first capacitor and the second capacitor. For example, the first switching component may be activated, a reference voltage may be applied to the sense component, and the first switching component may then be deactivated. In some examples, a voltage offset may be measured across both the first and the second capacitor.

First claim

What is claimed is:

1. A method for operating a memory array, comprising:
applying a reference voltage to a sense component;
activating a first switching component via a first signal after applying the reference voltage, the activation of the first switching component establishing a first conductive path between a first node and a voltage source; and
activating a second switching component via a second signal after the first switching component is activated, the activation of the second switching component establishing a second conductive path between the memory array and the sense component.

2. The method of claim 1 , further comprising:
deactivating the first switching component via the first signal after the first switching component is activated;
reactivating the first switching component via the first signal after the second switching component is activated; and
activating a third switching component and a fourth switching component via a third signal after the first switching component is reactivated.

3. The method of claim 2 , further comprising:
amplifying a signal from the memory array based at least in part on activating the third switching component and the fourth switching component.

4. The method of claim 2 , further comprising:
decreasing, based at least in part on reactivating the first switching component, a first voltage associated with the first node that is coupled to at least the third switching component and a first capacitor, a second voltage associated with a second node that is coupled to at least the first capacitor and a second capacitor, and a third voltage associated with a third node that is coupled to at least the fourth switching component and the second capacitor.

5. The method of claim 4 , further comprising:
measuring, based at least in part on the applied reference voltage, a voltage offset across both the first capacitor and the second capacitor.

6. The method of claim 1 , further comprising:
inducing a current across a first transistor of the sense component and a second transistor of the sense component based at least in part on activating the first switching component; and
decreasing, based at least in part on the induced current, a first voltage associated with the first node that is coupled to at least the first transistor and a first capacitor, and a second voltage associated with a second node that is coupled to at least the second transistor and a second capacitor.

7. The method of claim 6 , further comprising:
decreasing a third voltage associated with a third node that is coupled to at least the first capacitor and the second capacitor based at least in part on the first signal.

8. The method of claim 6 , wherein a threshold voltage of the first transistor is based at least in part on a difference between the reference voltage and the first voltage, and wherein a threshold voltage of the second transistor is based at least in part on a difference between the reference voltage and the second voltage.

9. An apparatus comprising:
a memory array; and
a memory controller in electronic communication with the memory array, wherein the memory controller is operable to:
apply a reference voltage to a sense component;
activate a first switching component via a first signal after applying the reference voltage, the activation of the first switching component establishing a first conductive path between a first node and a voltage source; and
activate a second switching component via a second signal after the first switching component is activated, the activation of the second switching component establishing a second conductive path between the memory array and the sense component.

10. The apparatus of claim 9 , wherein the memory controller is further operable to:
deactivate the first switching component via the first signal after the first switching component is activated;
reactivate the first switching component via the first signal after the second switching component is activated; and
activate a third switching component and a fourth switching component via a third signal after the first switching component is reactivated.

11. The apparatus of claim 10 , wherein the memory controller is further operable to:
amplify a signal from the memory array based at least in part on activation of the third switching component and the fourth switching component.

12. The apparatus of claim 10 , wherein the memory controller is further operable to:
decrease, based at least in part on reactivation of the first switching component, a first voltage associated with the first node that is coupled to at least the third switching component and a first capacitor, a second voltage associated with a second node that is coupled to at least the first capacitor and a second capacitor, and a third voltage associated with a third node that is coupled to at least the fourth switching component and the second capacitor.

13. The apparatus of claim 12 , wherein the memory controller is further operable to:
measure, based at least in part on the applied reference voltage, a voltage offset across both the first capacitor and the second capacitor.

14. The apparatus of claim 9 , wherein the memory controller is further operable to:
induce a current across a first transistor of the sense component and a second transistor of the sense component based at least in part on activating the first switching component; and
decrease, based at least in part on inducing the current, a first voltage associated with the first node that is coupled to at least the first transistor and a first capacitor, and a second voltage associated with a second node that is coupled to at least the second transistor and a second capacitor.

15. The apparatus of claim 14 , wherein the memory controller is further operable to:
decrease a third voltage associated with a third node that is coupled to at least the first capacitor and the second capacitor based at least in part on the first signal.

16. The apparatus of claim 14 , wherein a threshold voltage of the first transistor is based at least in part on a difference between the reference voltage and the first voltage, and wherein a threshold voltage of the second transistor is based at least in part on a difference between the reference voltage and the second voltage.

17. A method for operating a memory array, comprising:
charging a first node to a first voltage upon activating a first switching component and a second switching component, wherein a first capacitor is coupled to both the first node and the first switching component;
charging a second node to a second voltage upon activating the first switching component and a third switching component, wherein a second capacitor is coupled to both the second node and the first switching component;
charging both the first node and the second node to a third voltage upon activating a fourth switching component and a fifth switching component and upon deactivating the first switching component; and
measuring a voltage offset across both the first capacitor and the second capacitor upon charging both the first node and the second node to the third voltage.

18. The method of claim 17 , further comprising:
coupling the first capacitor to a sense amplifier via a first transistor of the sense amplifier; and
coupling the second capacitor to the sense amplifier via a second transistor of the sense amplifier.

19. The method of claim 18 , wherein a charge stored in the first capacitor is based at least in part on a threshold volt

Assignees

• Micron Technology Inc

Inventors

• Vimercati Daniele

Classifications

• G11C11/2273 Primary

  Reading or sensing circuits or methods · CPC title

• G11C29/026

  in sense amplifiers · CPC title

• G11C2029/0409

  Online test · CPC title

• G11C7/065

  Differential amplifiers of latching type · CPC title

• G11C11/4091

  Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating · CPC title