Sense amplifier having offset cancellation

Patent metadata

Field	Value
Publication number	US-10692565-B2
Application number	US-201916707738-A
Country	US
Kind code	B2
Filing date	Dec 9, 2019
Priority date	Dec 28, 2016
Publication date	Jun 23, 2020
Grant date	Jun 23, 2020

Abstract

A sense amplifier includes a sense amplifying unit, first and second isolation units, and first and second offset cancellation unit. The sense amplifying unit includes a first P-type metal-oxide-semiconductor (PMOS) transistor, a second PMOS transistor, a first N-type metal-oxide-semiconductor (NMOS) transistor, and a second NMOS transistor. In a layout of the sense amplifier, the first and second PMOS transistors are disposed in a central region of the sense amplifier, the first and second NMOS transistors are disposed at opposite sides of the sense amplifier from each other, the first isolation unit and the first offset cancellation unit are disposed between the first PMOS transistor and the first NMOS transistor, and the second isolation unit and the second offset cancellation unit are disposed between the second PMOS transistor and the second NMOS transistor. In other layouts, the locations of the PMOS transistors and NMOS transistors may be reversed.

First claim

What is claimed is:

1. A dynamic random access memory (DRAM) device, the DRAM device comprising:
a substrate;
a first conduction line pattern on the substrate;
a second conduction line pattern on the substrate;
a sense amplifier pattern electrically connected to the first conduction line pattern and the second conduction line pattern on the substrate;
wherein the sense amplifier pattern comprises:
a first active pattern including a first gate pattern electrically connected to the first conduction line pattern, the first gate pattern with a first width being aligned in a first direction;
a second active pattern disposed to be separated from the first active pattern in the first direction, the second active pattern including a second gate pattern and a third gate pattern being apart from the second gate pattern, the second gate pattern and the third gate pattern with a second width being substantially parallel to each other and respectively aligned in a second direction, the second direction being substantially perpendicular to the first direction;
a third active pattern disposed to be separated from the second active pattern in the first direction, the third active pattern including a fourth gate pattern and a fifth gate pattern being apart from the fourth gate pattern, the fourth gate pattern and the fifth gate pattern with a third width respectively aligned in the first direction;
a fourth active pattern disposed to be separated from the third active pattern in the first direction, the fourth active pattern including a sixth gate pattern and a seventh gate pattern being apart from the sixth gate pattern in the first direction, the sixth gate pattern and the seventh gate pattern with a fourth width being substantially parallel to each other and aligned in the second direction; and
a fifth active pattern disposed to be separated from the fourth active pattern in the first direction, the fifth active pattern including an eighth gate pattern electrically connected to the second conduction line pattern, the eighth gate pattern with a fifth width being substantially aligned in the first direction,
wherein the first width of the first gate pattern is relatively larger than the second width of the second gate pattern,
wherein the first width of the first gate pattern is relatively larger than the fourth width of the seventh gate pattern, and
wherein the first gate pattern, the second gate pattern, the third gate pattern, the fourth gate pattern, the fifth gate pattern, the sixth gate pattern, the seventh gate pattern and the eighth gate pattern respectively constitutes a first N-type metal oxide semiconductor (NMOS) transistor, a first offset cancellation transistor, a first isolation transistor, a first P-type metal oxide semiconductor (PMOS) transistor, a second PMOS transistor, a second isolation transistor, a second offset cancellation transistor and a second NMOS transistor.

2. The DRAM device of claim 1 , wherein the first width of the first gate pattern is relatively larger than the third width of the fourth gate pattern and the first width of the first gate pattern is substantially the same as the fifth width of the eighth gate pattern.

3. The DRAM device of claim 1 , wherein the first, fourth, fifth, and eighth gate patterns have extruded pattern portions at both end portions of the first, fourth, fifth, and eighth gate patterns, respectively.

4. The DRAM device of claim 1 , wherein the first conduction line pattern is a bit line pattern electrically connected to a first memory cell and the second conduction line pattern is a complementary bit line pattern electrically connected to a second memory cell.

5. The DRAM device of claim 1 , further comprising first and second terminal patterns disposed in the first active pattern at both sides of the first gate pattern,
wherein the first terminal pattern is electrically connected to a first control signal line pattern, and
the second terminal pattern is electrically connected to a complementary sensing bit line pattern.

6. The DRAM device of claim 1 , further comprising first and second terminal patterns disposed in the second active pattern at both sides of the second gate pattern and the third gate pattern, and
a third terminal pattern in the second active pattern between the second gate pattern and the third gate pattern,
wherein the first terminal pattern is electrically connected to a complementary sensing bit line pattern,
the second terminal pattern is electrically connected to a sensing bit line pattern,
the third terminal pattern is electrically connected to the first conduction line pattern,
the second gate pattern is electrically connected to an offset cancellation signal line pattern, and
the third gate pattern is electrically connected to an isolation signal line pattern.

7. The DRAM device of claim 6 , further comprising a ninth gate pattern in the second active pattern, the ninth gate pattern being apart from the third gate pattern, the ninth gate pattern being substantially aligned in the second direction; and
a fourth terminal pattern and the second terminal pattern disposed in the second active pattern at both sides of the ninth gate pattern,
wherein the ninth gate pattern is electrically connected to an equalizing signal line pattern, and
the fourth terminal pattern is electrically connected to a precharge voltage line pattern.

8. The DRAM device of claim 1 , further comprising first and second terminal patterns disposed in the third active pattern at both sides of the fourth gate pattern, and
third and fourth terminal patterns disposed in the third active pattern at both sides of the fifth gate pattern,
wherein the first terminal pattern is electrically connected to a second control signal line pattern,
the second terminal pattern is electrically connected to a complementary sensing bit line pattern,
the fourth gate pattern is electrically connected to a sensing bit line pattern,
the third terminal pattern is electrically connected to the second control signal line pattern and the first terminal pattern,
the fourth terminal pattern is electrically connected to the sensing bit line pattern, and
the fifth gate pattern is electrically connected to the complementary sensing bit line pattern.

9. The DRAM device of claim 1 , further comprising first and second terminal patterns disposed in the fourth active pattern at both sides of the sixth gate pattern and the seventh gate pattern, and
a third terminal pattern in the fourth active pattern between the sixth gate pattern and the seventh gate pattern,
wherein the first terminal pattern is electrically connected to a complementary sensing bit line pattern,
the sixth gate pattern is electrically connected to an isolation signal line pattern,
the third terminal pattern is electrically connected to the second conduction line pattern,
the seventh gate pattern is electrically connected to an offset cancellation signal line pattern, and
the second terminal pattern is electrically connected to a sensing bit line pattern.

10. The DRAM device of claim 9 , further comprising a tenth gate pattern in the fourth active pattern, the tenth gate pattern being apart from the sixth gate pattern, the tenth gate pattern being aligned in the second direction; and
a fourth terminal pattern and the first terminal pattern disposed in the second active pattern at both sides of the tenth gate pattern,
wherein the tenth gate pattern is electrically connected to an equalizing signal line pattern, and
the fourth terminal pattern is electrically connected to a precharge voltage line pattern.

11. The DRAM device of claim 1 , further comprising first and second termi

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Young-Wook
• Kwon Hyuk-Joon
• Han Sang-Keun
• Won Bok-Yeon

Classifications

• G11C11/4097

  Bit-line organisation, e.g. bit-line layout, folded bit lines · CPC title

• G11C11/4091 Primary

  Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating · CPC title

• G11C7/1048

  Data bus control circuits, e.g. precharging, presetting, equalising · CPC title

• G11C7/06

  Sense amplifiers; Associated circuits {, e.g. timing or triggering circuits} · CPC title

• G11C7/18 Primary

  Bit line organisation; Bit line lay-out · CPC title