Hybrid hysteretic control system

Patent metadata

Field	Value
Publication number	US-11888482-B2
Application number	US-202117565110-A
Country	US
Kind code	B2
Filing date	Dec 29, 2021
Priority date	Dec 29, 2021
Publication date	Jan 30, 2024
Grant date	Jan 30, 2024

Abstract

A system comprises a first comparator, a second comparator, a pulse-width modulation (PWM) controller, and a ramp generator. The first comparator has a positive input coupled to a first ramp output of the ramp generator and a negative input configured to receive an input voltage. The second comparator has a positive input configured to receive the input voltage and a negative input coupled to a second ramp output of the ramp generator. The PWM controller is coupled to outputs and control signal inputs of the first and second comparators and has a control output. In some implementations, the ramp generator generates a high-side falling ramp for the first comparator and a low-side rising ramp for the second comparator. In some implementations, the ramp generator includes a first ramp generator for the high-side falling ramp and a second ramp for the low-side rising ramp.

First claim

What is claimed is:

1. A system, comprising:
a first comparator having a first positive input, a first negative input, a first control input, and a first output;
a second comparator having a second positive input, a second negative input, a second control input, and a second output;
a pulse-width modulation (PWM) controller coupled to the first and second outputs and the first and second control inputs and having a control output;
a ramp generator having a first ramp output coupled to the first positive input and a second ramp output coupled to the second negative input;
an analog-to-digital converter (ADC) having an ADC output;
an adder having a positive input, a negative input coupled to the ADC output, and an adder output; and
a voltage controller having an input coupled to the adder output and an output coupled to the ramp generator.

2. The system of claim 1 , wherein the ramp generator is configured to generate a first ramp for the first comparator and a second ramp for the second comparator, wherein the first ramp is a high-side falling ramp, and wherein the second ramp is a low-side rising ramp.

3. The system of claim 2 , wherein the ramp generator comprises:
a first ramp generator having the first ramp output and configured to generate the first ramp for the first comparator; and
a second ramp generator having the second ramp output and configured to generate the second ramp for the second comparator.

4. The system of claim 2 , wherein the first and second ramps are offset by half a period T.

5. The system of claim 2 , wherein a first control signal generated by the PWM controller and provided to the first control input causes the first ramp to reset, and wherein a second control signal generated by the PWM controller and provided to the second control input causes the second ramp to reset.

6. The system of claim 1 , further comprising a voltage sensing circuit configured to provide an input voltage.

7. The system of claim 6 , wherein the input voltage is a first input voltage, wherein the control output comprises a first control output and a second control output, the system further comprising:
a first transistor having a first control terminal coupled to the first control output, a first current terminal, and a second current terminal;
a second transistor having a second control terminal coupled to the second control output, a third current terminal coupled to the second current terminal, and a fourth current terminal;
a capacitor having a first capacitor terminal coupled to the fourth current terminal and a second capacitor terminal;
an inductor having a first inductor terminal coupled to the second and third current terminals and a second inductor terminal;
a transformer having a first input coupled to the second inductor terminal, a second input coupled to the second capacitor terminal, a first transformer output, a second transformer output, and a third transformer output;
a third transistor having a third control terminal, a fifth current terminal coupled to the first transformer output, and a sixth current terminal; and
a fourth transistor having a fourth control terminal, a seventh current terminal coupled to the second transformer output, and an eighth current terminal coupled to the sixth current terminal.

8. The system of claim 7 , wherein the transformer is a center-tap transformer.

9. The system of claim 7 , wherein
the analog-to-digital converter (ADC) is configured to receive a voltage across the third transformer output and the sixth and eighth current terminals.

10. The system of claim 9 , wherein:
The ramp generator is configured to generate a first ramp for the first comparator and a second ramp for the second comparator; and
the voltage controller is configured to indicate a first initial frequency for the first ramp and a second initial frequency for the second ramp.

11. A device, comprising:
a first comparator having a first input configured to receive a first ramp and a second input configured to receive an input voltage, wherein the first comparator is configured to generate a first triggering signal;
a second comparator having a first input configured to receive the input voltage and a second input configured to receive a second ramp, wherein the second comparator is configured to generate a second triggering signal;
a pulse-width modulation (PWM) controller configured to generate a first control signal and a second control signal based on the first and second triggering signals;
a ramp generator configured to generate the first ramp for the first comparator and the second ramp for the second comparator;
an analog-to-digital converter (ADC) having an ADC output;
an adder having a first input, a second input coupled to the ADC output, and an adder output; and
a voltage controller having an input coupled to the adder output and an output coupled to the ramp generator.

12. The device of claim 11 , wherein the first ramp is a high-side falling ramp and the second ramp is a low-side rising ramp.

13. The device of claim 12 , wherein the first and second ramps are offset by half a period T.

14. The device of claim 11 , wherein:
the first comparator further comprises a first control input configured to receive a first feedback signal; and
the second comparator further comprises a second control input configured to receive a second feedback signal.

15. The device of claim 14 , wherein the PWM controller is further configured to generate the first feedback signal for the first comparator and the second feedback signal for the second comparator.

16. The device of claim 11 , wherein the input voltage is a first input voltage, the device further comprising:
a first transistor having a control terminal configured to receive the first control signal, a first current terminal, and a second current terminal;
a second transistor having a control terminal configured to receive the second control signal, a third current terminal coupled to the second current terminal, and a fourth current terminal, wherein the first and fourth current terminals are configured to receive a second input voltage;
a transformer having a first transformer input, a second transformer input, a first transformer output, a second transformer output, and a third transformer output;
a capacitor coupled between the fourth current terminal and the second transformer input;
a voltage sensing circuit configured to measure the first input voltage across the capacitor;
an inductor coupled between the second and third current terminals and the second transformer input;
a third transistor having a control terminal configured to receive a biasing voltage, a fifth current terminal coupled to the first transformer output, and a sixth current terminal; and
a fourth transistor having a control terminal configured to receive the biasing voltage, a seventh current terminal coupled to the second transformer output, and an eighth current terminal coupled to the sixth current terminal.

17. The device of claim 16 , wherein the transformer is a center-tap transformer.

18. The device of claim 11 , further comprising:
a first transistor having a control terminal configured to receive the first control signal, a first current terminal, and a second current terminal;
a second transistor having a control terminal configured to receive the second control signal, a third current terminal, and a fourth current terminal coupled to the first current terminal;
a capacitor having a first capacitor terminal coupled to the second current terminal an

Assignees

• Texas Instruments Inc

Inventors

• Jiang Chen
• Choudhury Shamim
• Akondy Subrahmanya Bharathi

Classifications

• H03K3/017 Primary

  Adjustment of width or dutycycle of pulses (pulse width modulation H03K7/08 {; to maintain energy constant H03K3/015}) · CPC title

• H03K3/023

  by the use of differential amplifiers or comparators, with internal or external positive feedback · CPC title

• H03K4/08

  having sawtooth shape · CPC title

• H03K17/56

  by the use, as active elements, of semiconductor devices (using diodes H03K17/74) · CPC title

• H02M1/08 Primary

  Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters · CPC title