Control circuit for buck-boost power converter with seamless mode transition control

Patent metadata

Field	Value
Publication number	US-2016352228-A1
Application number	US-201615166199-A
Country	US
Kind code	A1
Filing date	May 26, 2016
Priority date	May 26, 2015
Publication date	Dec 1, 2016
Grant date	—

Abstract

A buck-boost power converter and a control circuit for the buck-boost converter. The control circuit includes a buck cycle pulse width modulation module and a boost cycle pulse width modulation module respectively having a first controllable hysteresis and a second controllable hysteresis. The buck cycle pulse width modulation module can regulate the first controllable hysteresis during the buck-boost power converter transits between a buck mode and a buck-boost mode so as to eliminate or at least reduce sparks in an output voltage. The boost cycle pulse width modulation module can regulate the second controllable hysteresis during the buck-boost power converter transits between the buck-boost mode and a boost mode so as to eliminate or at least reduce sparks in the output voltage.

First claim

What is claimed is:

1 . A control circuit for regulating a buck-boost power converter, comprising:
an operational amplifier configured to receive a first feedback signal indicative of an output voltage of the buck-boost power converter and a reference signal, and further configured to conduct operation to the first feedback signal and the reference signal to provide an amplified difference signal indicative of a difference between the first feedback signal and the reference signal; a buck cycle pulse width modulation module configured to respectively receive the amplified difference signal and a first current sensing signal indicative of a switching current during a buck cycle of the buck-boost power converter, and to compare the first current sensing signal with the amplified difference signal to generate a first pulse width modulation signal for regulating a buck duty cycle of the buck-boost power converter, wherein the buck cycle pulse width modulation module has a first controllable hysteresis and a hysteresis control terminal which is configured to receive a first mode transition control signal, and wherein the buck cycle pulse width modulation module is further configured to enable the first controllable hysteresis in response to the first mode transition control signal when the buck-boost power converter transits from the buck mode to the buck-boost mode, and to disable the first controllable hysteresis in response to the first mode transition control signal when the buck-boost power converter transits from the buck-boost mode to the buck mode; and a boost cycle pulse width modulation module configured to respectively receive the amplified difference signal and a second current sensing signal indicative of a switching current during a boost cycle of the buck-boost power converter, and to compare the second current sensing signal with the amplified difference signal to generate a second pulse width modulation signal for regulating a boost duty cycle of the buck-boost power converter, wherein the boost cycle pulse width modulation module has a second controllable hysteresis and a hysteresis control terminal which is configured to receive a second mode transition control signal, and wherein the boost cycle pulse width modulation module is further configured to enable the second controllable hysteresis in response to the second mode transition control signal when the buck-boost power converter transits from the buck-boost mode to the boost mode, and to disable the second controllable hysteresis in response to the second mode transition control signal when the buck-boost power converter transits from the boost mode to the buck-boost mode.

2 . The control circuit of claim 1 , wherein
when the first controllable hysteresis is enabled, the buck cycle pulse width modulation module is configured to add the first controllable hysteresis to the amplified difference signal or to the first current sensing signal, and to compare the amplified difference signal with the first current sensing signal plus the first controllable hysteresis to decrease a pulse width of the first pulse width modulation signal; and wherein when the first controllable hysteresis is disabled, the buck cycle pulse width modulation module is configured to remove the first controllable hysteresis from the amplified difference signal or the first current sensing signal to increase a pulse width of the first pulse width modulation signal.

3 . The control circuit of claim 2 , wherein the control circuit is further configured to control a first power switch and a second power switch coupled in series between an input port of the buck-boost power converter and a reference ground, and a third power switch and a fourth power switch coupled in series between an output port of the buck-boost power converter and the reference ground, and wherein
the control circuit is further configured to increase an ON time of the second power switch and the fourth power switch in response to the decrease in the pulse width of the first pulse width modulation signal and to decrease the ON time of the second power switch and the fourth power switch in response to the increase in the pulse width of the first pulse width modulation signal, wherein an increment or a decrement in the ON time of the second power switch and the fourth power switch is set by designing a hysteresis value of the first controllable hysteresis.

4 . The control circuit of claim 1 , wherein
when the second controllable hysteresis is enabled, the boost cycle pulse width modulation module is configured to add the second controllable hysteresis to the amplified difference signal or to the second current sensing signal, and to compare the amplified difference signal with the second current sensing signal plus the second controllable hysteresis to decrease a pulse width of the second pulse width modulation signal; and wherein when the second controllable hysteresis is disabled, the boost cycle pulse width modulation module is configured to remove the second controllable hysteresis from the amplified difference signal or the second current sensing signal to increase a pulse width of the second pulse width modulation signal.

5 . The control circuit of claim 4 , wherein the control circuit is further configured to control a first power switch and a second power switch coupled in series between an input port of the buck-boost power converter and a reference ground, and a third power switch and a fourth power switch coupled in series between an output port of the buck-boost power converter and the reference ground, and wherein
the control circuit is further configured to decrease an ON time of the first power switch and the third power switch in response to the decrease in the pulse width of the second pulse width modulation signal and to increase the ON time of the first power switch and the third power switch in response to the increase in the pulse width of the second pulse width modulation signal, wherein an increment or a decrement in the ON time of the first power switch and the third power switch is set by designing a hysteresis value of the second controllable hysteresis.

6 . The control circuit of claim 1 , wherein the buck cycle pulse width modulation module comprises a first hysteresis comparison circuit having the first controllable hysteresis, and wherein the boost cycle pulse width modulation module comprises a second hysteresis comparison circuit having the second controllable hysteresis.

7 . The control circuit of claim 6 , wherein the first hysteresis comparison circuit comprises:
a first differential input stage comprising a first transistor, a second transistor, a third transistor, a first resistor, a second resistor, a third resistor and a first current source, wherein each of the first transistor, the second transistor and the third transistor has a first terminal, a second terminal and a control terminal, and wherein the first terminals of both the first transistor and the second transistor are coupled to the first current source to receive a first current, the control terminal of the first transistor is configured to receive the amplified difference signal while the control terminal of the second transistor is configured to receive the first current sensing signal, and the second terminal of the first transistor is coupled to a first terminal of the first resistor while the second terminal of the second transistor is coupled to a first terminal of the second resistor, and wherein a second terminal of the first resistor is coupled to the reference ground, and wherein a first terminal of the third resistor is coupled to a second terminal of the second resistor and a second terminal of the third resistor is coupled to the reference ground, and wherein the

Assignees

• Monolithic Power Systems Inc

Inventors

• Zhang Jian

Classifications

• H02M1/08

  Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters · CPC title

• H02M3/1582 Primary

  Buck-boost converters (H02M3/1584 takes precedence) · CPC title

• H02M2001/0009

  Electricity · mapped topic

• H02M1/32

  Means for protecting converters other than automatic disconnection · CPC title

• H02M1/0009

  Devices or circuits for detecting current in a converter · CPC title