Voltage-controlled magnetic anisotropy memory device including an anisotropy-enhancing dust layer and methods for forming the same

Patent metadata

Field	Value
Publication number	US-11887640-B2
Application number	US-202117341119-A
Country	US
Kind code	B2
Filing date	Jun 7, 2021
Priority date	Jun 7, 2021
Publication date	Jan 30, 2024
Grant date	Jan 30, 2024

Abstract

A magnetoelectric memory device includes a magnetic tunnel junction located between a first electrode and a second electrode. The magnetic tunnel junction includes a reference layer, a nonmagnetic tunnel barrier layer, a free layer, and a dielectric capping layer. At least one layer that provides voltage-controlled magnetic anisotropy is provided within the magnetic tunnel junction, which may include a pair of nonmagnetic metal dust layers located on, or within, the free layer, or a two-dimensional metal compound layer including a compound of a nonmagnetic metallic element and a nonmetallic element.

First claim

What is claimed is:

1. A magnetoelectric memory device, comprising:
a first electrode;
a second electrode; and
a magnetic tunnel junction located between the first electrode and the second electrode, the magnetic tunnel junction comprising, along a direction from the first electrode toward the second electrode, a first reference layer, a nonmagnetic tunnel barrier layer, and a free layer; and
a dielectric capping layer located between the magnetic tunnel junction and the second electrode,
wherein a two-dimensional metal compound layer including a two-dimensional compound of a nonmagnetic metallic element and a nonmetallic element is embedded within the free layer or is located between the nonmagnetic tunnel barrier layer and the free layer.

2. The memory device of claim 1 , wherein:
the nonmetallic element is selected from oxygen, chlorine, sulfur, selenium, tellurium, or silicon; and
the nonmagnetic metallic element is selected from iridium, platinum, palladium, rhodium, or ruthenium.

3. The memory device of claim 2 , wherein the nonmagnetic metallic element is iridium.

4. The memory device of claim 3 , wherein the two-dimensional metal compound layer consists essentially of iridium oxide having a rutile structure.

5. The memory device of claim 1 , wherein an atomic ratio of the nonmetallic element to the nonmagnetic metallic element is greater than 1.

6. The memory device of claim 1 , wherein the two-dimensional metal compound layer has in-plane covalent bonding and out-of-plane van der Waals bonding.

7. The memory device of claim 1 , wherein the two-dimensional metal compound layer contacts the nonmagnetic tunnel barrier layer and the free layer.

8. The memory device of claim 1 , wherein the free layer comprises:
a first component free layer in contact with the nonmagnetic tunnel barrier layer and the two-dimensional metal compound layer; and
a second component free layer in contact with the two-dimensional metal compound layer and the dielectric capping layer.

9. The memory device of claim 1 , wherein the two-dimensional metal compound layer consists essentially of a single nonmagnetic metallic element and a single nonmetallic element selected from oxygen, chlorine, sulfur, selenium, tellurium, and silicon.

10. The memory device of claim 1 , wherein a thickness to dielectric constant ratio of the dielectric capping layer is greater than a thickness to dielectric constant ratio of the nonmagnetic tunnel barrier layer, and wherein the magnetoelectric memory device comprises a voltage-controlled magnetic anisotropy memory device.

11. The memory device of claim 1 , further comprising a nonmagnetic metallic capping layer contacting the dielectric capping layer and the second electrode.

12. The memory device of claim 1 , further comprising a first composite reference magnetization structure located between the first electrode and the nonmagnetic tunnel barrier layer and including, along a direction from the first electrode toward the second electrode, a fixed vertical magnetization structure configured to generate a fixed vertical magnetic field at a planar end surface, a first nonmagnetic spacer metal layer located at the planar end surface, and the first reference layer.

13. The memory device of claim 12 , wherein the a fixed vertical magnetization structure comprises a composite synthetic antiferromagnet (SAF) structure including a first superlattice, a second superlattice, and an antiferromagnetic coupling layer having a thickness that provides antiferromagnetic coupling between the first superlattice and the second superlattice, wherein the first superlattice comprises a first superlattice of first ferromagnetic layers and first nonferromagnetic layers, and the second superlattice comprises a second superlattice of second ferromagnetic layers and second nonferromagnetic layers.

14. The memory device of claim 1 , further comprising a second reference layer in contact with the dielectric capping layer and having a same magnetization direction as the first reference layer.

15. The memory device of claim 1 , wherein the two-dimensional metal compound layer is embedded within the free layer.

16. The memory device of claim 1 , wherein the two-dimensional metal compound layer is located between the nonmagnetic tunnel barrier layer and the free layer.

17. The memory device of claim 16 , further comprising a second two-dimensional metal compound layer embedded within the free layer and including a two-dimensional compound of a nonmagnetic metallic element and a nonmetallic element having in-plane covalent bonding and out-of-plane van der Waals bonding.

18. The memory device of claim 1 , wherein the two-dimensional metal compound layer has a thickness in a range from 0.3 nm to 2 nm.

19. The memory device of claim 1 , further comprising a control circuit configured:
to perform a sensing operation that determines a magnetization state of the free layer by applying a sense voltage across the second electrode and the first electrode and by measuring magnetoresistance of the magnetic tunnel junction;
to perform a comparison operation that determines whether the magnetization state of the free layer is at a target magnetization state selected from an upward-pointing magnetization state and a downward-pointing magnetization state; and
to apply a programming pulse across the second electrode and the first electrode only if the magnetization state of the free layer is not the target magnetization state, and not to apply the programming pulse if the magnetization state of the free layer is the target magnetization state.

20. The memory device of claim 1 , wherein the programming pulse has a same polarity for programming the upward-pointing magnetization state into the downward-pointing magnetization state and for programming the downward-pointing magnetization state into the upward-pointing magnetization state.

Assignees

• Western Digital Tech Inc

Inventors

• Stewart Derek
• Kalitsov Alan
• Prasad Bhagwati

Classifications

• H10N50/85

  Materials of the active region · CPC title

• G11C11/161 Primary

  details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell · CPC title

• G11C11/1675

  Writing or programming circuits or methods · CPC title

• H01F10/3254

  the spacer being semiconducting or insulating, e.g. for spin tunnel junction [STJ] · CPC title

• H01F10/3272

  by use of anti-parallel coupled [APC] ferromagnetic layers, e.g. artificial ferrimagnets [AFI], artificial [AAF] or synthetic [SAF] anti-ferromagnets · CPC title