Memory channels calibration during boot wherein channels are calibrated in parallel based on identifer

Patent metadata

Field	Value
Publication number	US-11875871-B2
Application number	US-202218054056-A
Country	US
Kind code	B2
Filing date	Nov 9, 2022
Priority date	Dec 17, 2019
Publication date	Jan 16, 2024
Grant date	Jan 16, 2024

Abstract

In an embodiment, a system includes an energy source and an integrated circuit that is coupled to one or more memory devices via a plurality of memory channels. A memory controller in the integrated circuit is programmable with a plurality of identifiers corresponding to the plurality of channels, and is further programmable with a command and a first identifier associated with the command. Responsive to the command, the memory controller is configured to perform one or more calibrations on a subset of the plurality of channels for which corresponding identifiers of the plurality of identifiers match the first identifier. Other ones of the plurality of channels, for which the corresponding identifiers do not match the first identifier, do not perform the calibration.

First claim

What is claimed is:

1. A method comprising:
reading a charge state from an energy source in an electronic device during boot of the electronic device, wherein the charge state is indicative of available energy that the energy source is capable of supplying to the electronic device;
determining a number of a plurality of memory channels to calibrate in parallel based on the charge state;
triggering a calibration on the number of the plurality of memory channels in parallel while a remaining number of the plurality of memory channels are idle; and
repeating the reading, determining, and triggering for one or more additional iterations until the plurality of memory channels are calibrated.

2. The method as recited in claim 1 wherein the number of the plurality of memory channels on a first iteration and the number of the plurality of memory channels on a second iteration differ when the charge state differs.

3. The method as recited in claim 1 wherein triggering the calibration comprises:
programming selected channels of the plurality of memory channels to be calibrated in parallel with an identifier, wherein non-selected channels of the plurality of memory channels are not programmed with the identifier; and
transmitting a command including the identifier to trigger the calibration.

4. The method as recited in claim 3 wherein transmitting the command comprises:
writing the command including the identifier to a memory controller that includes the plurality of memory channels; and
broadcasting the command with the identifier by the memory controller to control circuitry associated with the plurality of memory channels.

5. The method as recited in claim 4 further comprising:
comparing the identifier to a first identifier programmed into a first channel of the plurality of memory channels by a first control circuit associated with the first channel.

6. The method as recited in claim 5 further comprising:
performing the calibration responsive to a match in the comparing; and
responding with a result of the calibration responsive to completing the calibration.

7. The method as recited in claim 5 further comprising responding with an identifier mismatch indication responsive to a mismatch in the comparing.

8. An electronic device comprising:
an energy source;
one or more memory devices; and
an integrated circuit configure to receive energy from the energy source, wherein:
the integrated circuit includes a memory controller coupled to the one or more memory devices,
the memory controller comprises a calibration control circuit configured to perform one or more memory calibrations during a boot of the electronic device,
the integrated circuit is configured to read a charge state indicative of available energy that the energy source is capable of supplying to the electronic device,
the memory controller is configured to modify the one or more memory calibrations based on the charge state.

9. The electronic device as recited in claim 8 wherein the integrated circuit includes at least one processor configured to execute a plurality of instructions forming a boot code during the boot of the electronic device, wherein the processor is configured to cause the integrated circuit to read the charge state based on an execution of the boot code.

10. The electronic device as recited in claim 9 wherein the at least one processor is configured to program the memory controller to modify the one or more memory calibrations based on the charge state and based on the execution of the boot code.

11. The electronic device as recited in claim 8 wherein the integrated circuit is configured to program the memory controller to modify the one or more memory calibrations based on the charge state.

12. The electronic device as recited in claim 11 wherein the memory controller is coupled to the one or more memory devices through a plurality of channels, and the integrated circuit is configured to modify the one or more memory calibrations by selecting a subset of the plurality of channels to perform the one or more memory calibrations in parallel.

13. The electronic device as recited in claim 12 wherein the integrated circuit is configured to iteratively read the charge state and perform the one or more memory calibrations on respective subsets of the plurality of channels until the one or more memory calibrations have been completed on the plurality of channels.

14. The electronic device as recited in claim 13 wherein the memory controller comprises a plurality of channel control circuits, wherein a given channel control circuit of the plurality of channel control circuits is coupled to a respective channel of the plurality of channels, and the given channel control circuit is configured to perform the one or more memory calibrations on the respective channel.

15. The electronic device as recited in claim 14 wherein each of the plurality of channel control circuits is programmable with an identifier, and wherein the calibration control circuit is configured to program the subset of the plurality of channels with a same first value, and wherein the calibration control circuit is configured to broadcast a command including the first value to the plurality of channel control circuits to cause the subset of the plurality of channel control circuits to perform the one or more memory calibrations while remaining ones of the plurality of channel control circuits that are not in the subset do not perform the one or more memory calibrations.

16. The electronic device as recited in claim 15 wherein the given channel control circuit is configured to respond to the command with a result of the calibration based on a match between the first value programmed in the given channel control circuit and the first value in the command.

17. The electronic device as recited in claim 16 wherein a second given channel control circuit in the remaining ones of the plurality of channel control circuits is configured to respond to the command with an identifier mismatch response.

18. The electronic device as recited in claim 16 wherein the calibration control circuit is configured to collect responses from the plurality of channel control circuits and to generate a composite response from the responses, wherein the composite response is error based on the response from at least one of the plurality of channel control circuits indicating error, and wherein the composite response is complete based on none of the responses from the plurality of channel control circuits indicating error.

19. A memory controller comprising:
a control circuit comprising a command register; and
a plurality of channel control circuits coupled to the control circuit, wherein:
a given channel control circuit of the plurality of channel control circuits is configure to perform one or more memory calibrations on a respective channel of a plurality of channels to one or more memory devices controlled by the memory controller,
the given channel control circuit is configured to selectively perform the one or more memory calibrations based on a command programmed into command register,
the command is programmed based a charge state of an energy source that supplies energy to an electronic device including the memory controller, and
the charge state is indicative of available energy that the energy source is capable of supplying to the electronic device.

20. The memory controller as recited in claim 19 wherein the given channel control circuit is programmable with a fir

Assignees

• Apple Inc

Inventors

• Jeter Robert E
• Notani Rakesh L
• Juarez Dominguez Alma L

Classifications

• G11C5/148 Primary

  Details of power up or power down circuits, standby circuits or recovery circuits · CPC title

• G06F3/0604

  Improving or facilitating administration, e.g. storage management · CPC title

• G06F3/0632

  by initialisation or re-initialisation of storage systems · CPC title

• G06F3/0659

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• G06F3/0673

  Single storage device · CPC title