Memory channels calibration during boot wherein channels are calibrated in parallel based on identifers

Patent metadata

Field	Value
Publication number	US-11527269-B2
Application number	US-201916716616-A
Country	US
Kind code	B2
Filing date	Dec 17, 2019
Priority date	Dec 17, 2019
Publication date	Dec 13, 2022
Grant date	Dec 13, 2022

Abstract

In an embodiment, a system includes an energy source and an integrated circuit that is coupled to one or more memory devices via a plurality of memory channels. A memory controller in the integrated circuit is programmable with a plurality of identifiers corresponding to the plurality of channels, and is further programmable with a command and a first identifier associated with the command. Responsive to the command, the memory controller is configured to perform one or more calibrations on a subset of the plurality of channels for which corresponding identifiers of the plurality of identifiers match the first identifier. Other ones of the plurality of channels, for which the corresponding identifiers do not match the first identifier, do not perform the calibration.

First claim

What is claimed is:

1. A method comprising:
reading a charge state from an energy source in an electronic device during boot of the electronic device;
determining a number of a plurality of memory channels to calibrate in parallel based on the charge state;
triggering a calibration on the number of the plurality of memory channels in parallel while a remaining number of the plurality of memory channels are idle; and
repeating the reading, determining, and triggering for one or more additional iterations until the plurality of memory channels are calibrated, wherein triggering the calibration comprises:
programming selected channels of the plurality of memory channels to be calibrated in parallel with an identifier, wherein non-selected channels of the plurality of memory channels are not programmed with the identifier;
writing a command including the identifier to a memory controller that includes the plurality of memory channels; and
broadcasting the command with the identifier by the memory controller to control circuitry associated with the plurality of memory channels.

2. The method as recited in claim 1 wherein the number of the plurality of memory channels on a first iteration and the number of the plurality of memory channels on a second iteration differ when the charge state differs.

3. The method as recited in claim 1 further comprising:
comparing the identifier to a first identifier programmed into a first channel of the plurality of memory channels by a first control circuit associated with the first channel.

4. The method as recited in claim 3 further comprising:
performing the calibration responsive to a match in the comparing; and
responding with a result of the calibration responsive to completing the calibration.

5. The method as recited in claim 3 further comprising responding with an identifier mismatch indication responsive to a mismatch in the comparing.

6. A memory controller comprising:
a control circuit comprising a command register; and
a plurality of channel control circuits coupled to the control circuit, wherein:
a given channel control circuit of the plurality of channel control circuits includes an identifier register,
the given channel control circuit is coupled to a memory channel to a memory during use,
the identifier register is programmable with a first identifier,
the command register is programmable with a command and a second identifier,
the control circuit is configured to broadcast the command and the second identifier to the plurality of channel control circuits, and
the given channel control circuit is configured to perform a calibration on the memory channel responsive to the command and the second identifier matching the first identifier.

7. The memory controller as recited in claim 6 wherein the given channel control circuit is configured not to perform the calibration responsive to the command and the second identifier mismatching the first identifier.

8. The memory controller as recited in claim 7 wherein the given channel control circuit is configured to respond to the command with an identifier mismatch response responsive to the second identifier mismatching the first identifier.

9. The memory controller as recited in claim 8 wherein the given channel control circuit is configured to respond to the command with a result of the calibration.

10. The memory controller as recited in claim 9 wherein the control circuit is configured to collect responses from the plurality of channel control circuits and generate a composite response from the responses, wherein the control circuit is configured to write the composite response to the command register.

11. The memory controller as recited in claim 10 wherein the command register includes a first indication to cause the control circuit to perform the command, wherein the control circuit is configured to broadcast the command to the plurality of channel control circuits responsive to the first indication.

12. The memory controller as recited in claim 11 wherein the control circuit is configured to change the first indication responsive to writing the composite response to the command register to indicate that the command is complete.

13. The memory controller as recited in claim 10 wherein the composite response is error responsive to the response from at least one of the plurality of channel control circuits indicating error.

14. The memory controller as recited in claim 13 wherein the composite response is complete responsive to none of the responses from the plurality of channel control circuits indicating error.

15. The memory controller as recited in claim 6 wherein the plurality of channel control circuits are configured to perform the calibration in parallel responsive to the command and the second identifier having a predetermined value that is not matched to the first identifier.

16. A system comprising:
an energy source;
a power management unit coupled to the energy source;
one or more memory devices; and
an integrated circuit coupled to the power management unit, wherein the integrated circuit includes a plurality of channels coupled to the one or more memory devices, and wherein the integrated circuit comprises a memory controller coupled to the plurality of channels, wherein the memory controller is programmable with a plurality of identifiers corresponding to the plurality of channels, and wherein the memory controller is programmable with a command specifying one or more calibrations to be performed and a first identifier, wherein the memory controller is configured to broadcast the command and the first identifier to a plurality of channel control circuits coupled to the plurality of channels, and wherein the plurality of channel control circuits are configured to perform the one or more calibrations on a subset of the plurality of channels for which the first identifier matches a corresponding one of the plurality of identifiers while remaining ones of the plurality of channels that are not in the subset do not perform the calibration.

17. The system as recited in claim 16 wherein the integrated circuit includes at least one processor configured to execute a plurality of instructions to program the memory controller and to communicate with the power management unit to determine a charge state in the energy source to program the plurality of identifiers.

18. The system as recited in claim 16 wherein the energy source comprises a battery.

19. The system as recited in claim 16 wherein a given channel control circuit of the plurality of channel control circuits is configured to respond to the command with a result of the calibration based on a match between the first identifier and a corresponding identifier of the plurality of identifiers, and wherein the given channel control circuit is configured to respond to the command with an identifier mismatch response based on the first identifier mismatching with the corresponding identifier.

20. The system as recited in claim 19 wherein the given channel control circuit is configured to collect responses from the plurality of channel control circuits and generate a composite response from the responses, wherein the composite response is error responsive to the response from at least one of the plurality of channel control circuits indicating error, and wherein the composite response is complete responsive to none of the responses from the plurality of channel control circuits indicating error.

Assignees

• Apple Inc

Inventors

• Jeter Robert E
• Notani Rakesh L
• Juarez Dominguez Alma L

Classifications

• G11C5/148 Primary

  Details of power up or power down circuits, standby circuits or recovery circuits · CPC title

• G11C7/10

  Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers · CPC title

• G06F3/0659

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• G11C2207/2254

  Calibration · CPC title

• G11C29/022

  in I/O circuitry · CPC title