Cache coherent system including master-side filter and data processing system including same

Patent metadata

Field	Value
Publication number	US-2017004084-A1
Application number	US-201615198583-A
Country	US
Kind code	A1
Filing date	Jun 30, 2016
Priority date	Jul 1, 2015
Publication date	Jan 5, 2017
Grant date	—

Abstract

An application processor is provided. The application processor includes a cache coherent interconnect, a first master device connected to the cache coherent interconnect, a second master device, and a master-side filter connected between the cache coherent interconnect and the second master device. The master-side filter receives a snoop request from the first master device through the cache coherent interconnect, compares a second security attribute of the second master device with a first security attribute of the first master device which is included in the snoop request, and determines whether to transmit an address included in the snoop request to the second master device according to a comparison result.

First claim

1 . An application processor comprising:
a first master device having a first security attribute, a second master device having a second security attribute, and a master-side filter, each respectively interconnected by a cache coherent interconnect, wherein the first master device is configured to communicate a snoop request including a first snoop address and a security attribute indicator indicating the first security attribute, and the master-side filter is configured to execute a snoop operation by receiving the first snoop request from the first master device via the cache coherent interconnect, comparing the second security attribute with the first security attribute as indicated by the snoop request, determining not to communicate the first snoop address to the second master device when the first security attribute and the second security attribute are different, and determining to communicate the first snoop address to the second master device when the first security attribute and the second security attribute are the same.

2 . The application processor of claim 1 , wherein the first security attribute indicates either a secure mode or a non-secure mode for the first master device, and
the second security attribute indicates either the secure mode or the non-secure mode for the second master device.

3 . The application processor of claim 2 , wherein upon determining not to communicate the first snoop address to the second master device, the master-side filter is further configured to communicate a first cache miss to the first master device via the cache coherent interconnect.

4 . The application processor of claim 3 , wherein the second master device comprises:
a cache configured to store at least one address and data respectively corresponding to each one of the at least one address; and a cache controller configured to compare each one of the at least one address with the first snoop address when communicated from the master-side filter, and upon identifying a matching address for the first snoop address among the at least one address, communicating data corresponding to the matching address to the master-side filter, else communicating a second cache miss to the master-side filter.

5 . The application processor of claim 4 , wherein the master-side filter is further configured to communicate one of the first cache miss, the corresponding data, or the second cache miss to the first master device via the cache coherent interconnect.

6 . The application processor of claim 1 , further comprising:
a controller configured to determine the second security attribute in response to a control signal communicated from the first master device, wherein the controller is configured to communicate the second security attribute to the master-side filter using a dedicated transmission line.

7 . The application processor of claim 1 , wherein the master-side filter comprises:
a memory device configured to store the at least one address and for each one of the at least one address a corresponding memory region; and a decision logic circuit connected to the memory device and configured to compare the first security attribute and the second security attribute, and to compare the first snoop address with each one of the at least one address.

8 . The application processor of claim 7 , wherein upon determining that the first security attribute is the same as the second security attribute and upon determining that the first snoop address is the same as a matching address among the at least one address, the decision logic circuit is further configured to communicate the first snoop address to the second master device, and
upon determining that the first security attribute is different from the second security attribute or upon determining that the first snoop address is different from each one of the at least one address, the decision logic circuit is further configured to communicate a cache miss to the first master via the cache coherent interconnect.

9 . The application processor of claim 7 , wherein the memory device is further configured to store for each memory region a corresponding security attribute;
the decision logic circuit is further configured to determine whether the first security attribute is the same as the second security attribute, and whether a first security attribute corresponding to a memory region indicated by the first snoop address is the same as a second security attribute corresponding to a memory region indicated by a matching address among the at least one address, and the decision logic circuit only determines to communicate the first snoop address to the second master device if the first security attribute is the same as the second security attribute.

10 . The application processor of claim 2 , wherein the first master device is further configured to control operation of the second master device such that all secure data stored in a cache of second master device during secure mode operation is deleted when the second master device exits the secure mode and enters the non-secure mode.

11 . The application processor of claim 1 , further comprising a slave-side filter connected to the cache coherent interconnect and configured to access a main memory device in response to a memory access request received from the first master device,
wherein the slave-side filter cannot perform the snoop operation executed by the master-side filter.

12 . The application processor of claim 1 , wherein the first master device is a central processing circuit (CPU), and the second master device is one of a graphics processing unit (GPU), a general-purpose computing on graphics processing unit (GPGPU), and a digital signal processor (DSP).

13 . A data processing system comprising:
a controller connected to a main memory device disposed external to the controller, wherein the controller comprises; a first master device having a first security attribute, a second master device having a second security attribute, a master-side filter, and a slave-side filter, each respectively interconnected by a cache coherent interconnect, wherein the first master device is configured to communicate a snoop request including a first snoop address and a security attribute indicator indicating the first security attribute, and the master-side filter is connected between the cache coherent interconnect and the second master device and configured to execute a snoop operation by receiving the first snoop request from the first master device via the cache coherent interconnect, comparing the second security attribute with the first security attribute as indicated by the snoop request, determining not to communicate the first snoop address to the second master device when the first security attribute and the second security attribute are different, and determining to communicate the first snoop address to the second master device when the first security attribute and the second security attribute are the same, and the slave-side filter is connected between the cache coherent interconnect and the main memory device and configured to perform a memory access operation directed to the main memory device in response to a memory access request received from the first master device via the cache coherent interconnect.

14 . The data processing system of claim 13 , wherein the first security attribute indicates either a secure mode or a non-secure mode for the first master device,
the second security attribute indicates either the secure mode or the non-secure mode for the second master device, and upon determining not to communicate the first snoop

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Sik
• Chun Woo Hyung
• Jo Seong Min
• Hur Jae Young

Classifications

• G06F2212/621

  Coherency control relating to peripheral accessing, e.g. from DMA or I/O device · CPC title

• G06F12/1433

  for a module or a part of a module · CPC title

• G06F12/0831 Primary

  using a bus scheme, e.g. with bus monitoring or watching means · CPC title

• G06F2212/1052

  Security improvement · CPC title

• G06F12/0815 Primary

  Cache consistency protocols · CPC title