Voltage-controlled magnetic anisotropy memory device including an anisotropy-enhancing dust layer and methods for forming the same

Patent metadata

Field	Value
Publication number	US-11871679-B2
Application number	US-202117341049-A
Country	US
Kind code	B2
Filing date	Jun 7, 2021
Priority date	Jun 7, 2021
Publication date	Jan 9, 2024
Grant date	Jan 9, 2024

Abstract

A magnetoelectric memory device includes a magnetic tunnel junction located between a first electrode and a second electrode. The magnetic tunnel junction includes a reference layer, a nonmagnetic tunnel barrier layer, a free layer, and a dielectric capping layer. At least one layer that provides voltage-controlled magnetic anisotropy is provided within the magnetic tunnel junction, which may include a pair of nonmagnetic metal dust layers located on, or within, the free layer, or a two-dimensional metal compound layer including a compound of a nonmagnetic metallic element and a nonmetallic element.

First claim

What is claimed is:

1. A magnetoelectric memory device, comprising:
a first electrode;
a second electrode;
a magnetic tunnel junction located between the first electrode and the second electrode, the magnetic tunnel junction comprising, from a side of the first electrode toward the second electrode, a first reference layer, a nonmagnetic tunnel barrier layer, a first nonmagnetic metal dust layer, a free layer, and a second nonmagnetic metal dust layer; and
a dielectric capping layer located between the magnetic tunnel junction and the second electrode,
wherein the first nonmagnetic metal dust layer and the second nonmagnetic metal dust layer have opposite signs of a voltage-controlled magnetic anisotropy coefficient.

2. The memory device of claim 1 , wherein the magnetoelectric memory device comprises a voltage-controlled magnetic anisotropy memory device.

3. The memory device of claim 1 , wherein:
the first nonmagnetic metal dust layer consists essentially of a first nonmagnetic metal; and
the second nonmagnetic metal dust layer consists essentially of a second nonmagnetic metal that is different from the first nonmagnetic metal.

4. The memory device of claim 1 , wherein:
the first nonmagnetic metal dust layer comprises an iridium layer having a thickness in a range from 0.1 monolayer of iridium to 2 monolayers of iridium; and
the second nonmagnetic metal dust layer comprises a platinum layer having a thickness in a range from 0.1 monolayer of platinum to 2 monolayers of platinum.

5. The memory device of claim 1 , wherein:
the first nonmagnetic metal dust layer comprises a platinum layer having a thickness in a range from 0.1 monolayer of iridium to 2 monolayers of platinum; and
the second nonmagnetic metal dust layer comprises an iridium layer having a thickness in a range from 0.1 monolayer of platinum to 2 monolayers of iridium.

6. The memory device of claim 1 , wherein the first nonmagnetic metal dust layer and the second nonmagnetic metal dust layer are independently selected from Ir, Mg, Mg—Al, Pd, Pt, W, Ta, Hf, Ru, or Rh.

7. The memory device of claim 6 , wherein each of the nonmagnetic tunnel barrier layer and the dielectric capping layer comprises a respective material selected from magnesium oxide, a magnesium aluminum oxide spinel material or a ferroelectric metal oxide material.

8. The memory device of claim 1 , wherein a thickness to dielectric constant ratio of the dielectric capping layer is greater than a thickness to dielectric constant ratio of the nonmagnetic tunnel barrier layer.

9. The memory device of claim 1 , further comprising a nonmagnetic metallic capping layer located between the dielectric capping layer and the second electrode.

10. The memory device of claim 1 , further comprising a first composite reference magnetization structure located between the first electrode and the nonmagnetic tunnel barrier layer and including, along a direction from the first electrode toward the second electrode, a fixed vertical magnetization structure configured to generate a fixed vertical magnetic field at a planar end surface, a first nonmagnetic spacer metal layer located at the planar end surface, and the first reference layer.

11. The memory device of claim 10 , wherein the a fixed vertical magnetization structure comprises a composite synthetic antiferromagnet (SAF) structure including a first superlattice, a second superlattice, and an antiferromagnetic coupling layer having a thickness that provides antiferromagnetic coupling between the first superlattice and the second superlattice, wherein the first superlattice comprises a first superlattice of first ferromagnetic layers and first nonferromagnetic layers, and the second superlattice comprises a second superlattice of second ferromagnetic layers and second nonferromagnetic layers.

12. The memory device of claim 10 , wherein the first composite reference magnetization structure further comprises at least one first layer stack located between the first nonmagnetic spacer metal layer and the first reference layer, wherein each of the at least one first layer stack comprises a respective first additional reference layer including a respective ferromagnetic material having perpendicular magnetic anisotropy, and a respective first spacer dielectric metal oxide layer.

13. The memory device of claim 1 , further comprising a second reference layer located between the second electrode and the dielectric capping layer and having a same magnetization direction as the first reference layer.

14. The memory device of claim 13 , further comprising a composite reference magnetization structure located between the dielectric capping layer and the second electrode and including, along a direction from the dielectric capping layer toward the second electrode, the second reference layer, a nonmagnetic spacer metal layer, and a fixed vertical magnetization structure configured to generate a fixed vertical magnetic field at an interface with the nonmagnetic spacer metal layer.

15. The memory device of claim 1 , further comprising an external field source that is configured to apply an in-plane ancillary magnetic field to the free layer, wherein the in-plane ancillary magnetic field induces gyration of an azimuthal magnetization direction of the free layer upon application of an electric field between the first electrode and the second electrode.

16. The memory device of claim 1 , wherein:
the first nonmagnetic metal dust layer provides a first voltage-controlled magnetic anisotropy coefficient;
the second nonmagnetic metal dust layer provides a second voltage-controlled magnetic anisotropy coefficient; and
a magnitude of the second voltage-controlled magnetic anisotropy coefficient is at least 25% of a magnitude of the first voltage-controlled magnetic anisotropy coefficient.

17. The memory device of claim 1 , wherein:
at least one of the first nonmagnetic metal dust layer and the second nonmagnetic metal dust layer has a sub-monolayer thickness; and
the at least one of the first nonmagnetic metal dust layer and the second nonmagnetic metal dust layer includes openings therethrough or includes multiple clusters that do not contact one another.

18. The memory device of claim 1 , further comprising a control circuit configured:
to perform a sensing operation that determines a magnetization state of the free layer by applying a sense voltage across the second electrode and the first electrode and by measuring magnetoresistance of the magnetic tunnel junction;
to perform a comparison operation that determines whether the magnetization state of the free layer is at a target magnetization state selected from an upward-pointing magnetization state and a downward-pointing magnetization state; and
to apply a programming pulse across the second electrode and the first electrode only if the magnetization state of the free layer is not the target magnetization state, and not to apply the programming pulse if the magnetization state of the free layer is the target magnetization state.

19. The memory device of claim 18 , wherein the programming pulse has a same polarity for programming the upward-pointing magnetization state into the downward-pointing magnetization state and for programming the downward-pointing magnetization state into the upward-pointing magnetization state.

20. The memory device of claim 19 , wherein:
the sense voltage has a first polarity and generates a first electric field within the free layer along a direction that increases magnetic a

Assignees

• Western Digital Tech Inc

Inventors

• Kalitsov Alan
• Stewart Derek
• Prasad Bhagwati

Classifications

• H10N50/85

  Materials of the active region · CPC title

• H10N50/80 Primary

  Constructional details · CPC title

• G11C11/161 Primary

  details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell · CPC title

• G11C11/1673

  Reading or sensing circuits or methods · CPC title

• G11C11/1675

  Writing or programming circuits or methods · CPC title