Antenna apparatus and fabrication method

Patent metadata

Field	Value
Publication number	US-11870130-B2
Application number	US-202016939392-A
Country	US
Kind code	B2
Filing date	Jul 27, 2020
Priority date	Jul 27, 2020
Publication date	Jan 9, 2024
Grant date	Jan 9, 2024

Abstract

A semiconductor device includes a semiconductor die comprising a radio frequency (RF) circuit, a first dielectric layer disposed over a first surface of the semiconductor die, an antenna layer disposed over a surface of the first dielectric layer, and an antenna feeding structure coupling the antenna layer to the RF circuit of the semiconductor die, wherein the semiconductor die comprises a via, and the antenna feeding structure comprises a first portion arranged within the opening of the semiconductor die and extending to the first surface of the semiconductor die, and a second portion arranged through the first dielectric layer.

First claim

What is claimed is:

1. A semiconductor device comprising:
a semiconductor die comprising a radio frequency (RF) circuit;
a first dielectric layer disposed over a first surface of the semiconductor die;
an antenna layer disposed over a surface of the first dielectric layer; and
an antenna feeding structure coupling the antenna layer to the RF circuit of the semiconductor die, wherein:
the semiconductor die comprises an opening; and
the antenna feeding structure comprises:
a first portion comprising a first via arranged within the opening of the semiconductor die and extending to the first surface of the semiconductor die,
a second portion comprising a second via arranged through the first dielectric layer and extending from the first surface of the semiconductor die to the antenna layer, and
a third portion comprising a planar conductive feature disposed on the first surface of the semiconductor die, the third portion conductively connecting the first portion to the second portion.

2. The semiconductor device of claim 1 , wherein:
the first surface of the semiconductor die is a backside of the semiconductor die.

3. The semiconductor device of claim 2 , further comprising:
a redistribution structure over a second surface of the semiconductor die, wherein the redistribution structure is electrically coupled to the RF circuit, and the second surface of the semiconductor die is a front side of the semiconductor die; and
a plurality of input/output connectors electrically coupled to the semiconductor die through the redistribution structure.

4. The semiconductor device of claim 3 , wherein:
the redistribution structure comprises a redistribution layer and a second dielectric layer, and wherein the redistribution layer is embedded in the second dielectric layer.

5. The semiconductor device of claim 1 , wherein:
the first via extends partially through the semiconductor die; and
a bottommost end of the first via is connected to a contact embedded in the semiconductor die.

6. The semiconductor device of claim 1 , wherein:
the antenna layer extends over a sidewall of the semiconductor device, and wherein a bottommost level of a portion of the antenna layer extending over the sidewall of the semiconductor device is higher than the first surface of the semiconductor die.

7. The semiconductor device of claim 1 , wherein:
the semiconductor device is an antenna-in-package (AiP) device.

8. A method of using a semiconductor device comprising: a semiconductor die comprising a radio frequency (RF) circuit; a first dielectric layer disposed over a first surface of the semiconductor die; an antenna layer disposed over a surface of the first dielectric layer; and an antenna feeding structure coupling the antenna layer to the RF circuit of the semiconductor die, wherein the semiconductor die comprises an opening, and the antenna feeding structure comprises: a first portion comprising a first via arranged within the opening of the semiconductor die and extending to the first surface of the semiconductor die, a second portion comprising a second via arranged through the first dielectric layer and extending from the first surface of the semiconductor die to the antenna layer, and a third portion comprising a planar conductive feature disposed on the first surface of the semiconductor die, the third portion conductively connecting the first portion to the second portion, the method comprising:
generating a first RF signal using the RF circuit of the semiconductor die; and
coupling the first RF signal to the antenna layer via the antenna feeding structure.

9. The method of claim 8 , further comprising transmitting the first RF signal via the antenna layer.

10. The method of claim 8 , further comprising:
receiving a second RF signal via the antenna layer; and
coupling the second RF signal to the RF circuit of the semiconductor die via the antenna feeding structure.

11. The method of claim 8 , wherein the first surface of the semiconductor die is a backside of the semiconductor die.

12. The method of claim 11 , wherein the semiconductor device further comprises:
a redistribution structure over a second surface of the semiconductor die, wherein the redistribution structure is electrically coupled to the RF circuit, and the second surface of the semiconductor die is a front side of the semiconductor die; and
a plurality of input/output connectors electrically coupled to the semiconductor die through the redistribution structure.

13. The method of claim 12 , wherein:
the redistribution structure comprises a redistribution layer and a second dielectric layer, and wherein the redistribution layer is embedded in the second dielectric layer.

14. The method of claim 8 , wherein:
the first via extends partially through the semiconductor die; and
a bottommost end of the first via is connected to a contact embedded in the semiconductor die.

15. The method of claim 8 , wherein:
the antenna layer extends over a sidewall of the semiconductor device, and wherein a bottommost level of a portion of the antenna layer extending over the sidewall of the semiconductor device is higher than the first surface of the semiconductor die.

16. The method of claim 8 , wherein the semiconductor device is an antenna-in-package (AiP) device.

17. A method of forming a semiconductor device, the method comprising:
providing a semiconductor die comprising a radio frequency (RF) circuit;
forming a first dielectric layer disposed over a first surface of the semiconductor die;
forming an antenna layer disposed over a surface of the first dielectric layer; and
forming an antenna feeding structure coupling the antenna layer to the RF circuit of the semiconductor die, wherein:
the semiconductor die comprises an opening; and
the antenna feeding structure comprises:
a first portion comprising a first via arranged within the opening of the semiconductor die and extending to the first surface of the semiconductor die,
a second portion comprising a second via arranged through the first dielectric layer and extending from the first surface of the semiconductor die to the antenna layer, and
a third portion comprising a planar conductive layer disposed on the first surface of the semiconductor die, the third portion conductively connecting the first portion to the second portion.

18. The method of claim 17 , wherein the first surface of the semiconductor die is a backside of the semiconductor die.

19. The method of claim 18 , further comprising:
forming a redistribution structure over a second surface of the semiconductor die, wherein the redistribution structure is electrically coupled to the RF circuit, and the second surface of the semiconductor die is a front side of the semiconductor die; and
forming a plurality of input/output connectors electrically coupled to the semiconductor die through the redistribution structure.

20. The method of claim 19 , wherein:
the redistribution structure comprises a redistribution layer and a second dielectric layer, and wherein the redistribution layer is embedded in the second dielectric layer.

Assignees

• Infineon Technologies Ag

Inventors

• Cho Eung San
• Baheti Ashutosh
• Trotta Saverio

Classifications

• H10W44/248

  for antennas · CPC title

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W70/095

  of vias therein · CPC title

• H10W70/093

  Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps · CPC title

• H10W70/05

  of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04) · CPC title