Gate-all-around integrated circuit structures including varactors

Patent metadata

Field	Value
Publication number	US-11869987-B2
Application number	US-202217860056-A
Country	US
Kind code	B2
Filing date	Jul 7, 2022
Priority date	Mar 25, 2020
Publication date	Jan 9, 2024
Grant date	Jan 9, 2024

Abstract

Gate-all-around integrated circuit structures including varactors are described. For example, an integrated circuit structure includes a varactor structure on a semiconductor substrate. The varactor structure includes a plurality of discrete vertical arrangements of horizontal nanowires. A plurality of gate stacks is over and surrounding corresponding ones of the plurality of discrete vertical arrangements of horizontal nanowires. The integrated circuit structure also includes a tap structure adjacent to the varactor structure on the semiconductor substrate. The tap structure includes a plurality of merged vertical arrangements of horizontal nanowires. A plurality of semiconductor structures is over and surrounding corresponding ones of the plurality of merged vertical arrangements of horizontal nanowires.

First claim

What is claimed is:

1. An integrated circuit structure, comprising:
a varactor structure on a semiconductor island on a semiconductor substrate, the varactor structure comprising a plurality of discrete gate stacks on the semiconductor island;
a tap structure adjacent to the varactor structure on the semiconductor island, the tap structure comprising a plurality of merged gate stacks on the semiconductor island; and
a transistor structure on the semiconductor substrate, the transistor structure isolated from the semiconductor island, and the transistor structure comprising a plurality of merged vertical arrangements of horizontal nanowires, and a plurality of gate stacks over and surrounding corresponding ones of the plurality of merged vertical arrangements of horizontal nanowires.

2. The integrated circuit structure of claim 1 , wherein the plurality of merged vertical arrangements of horizontal nanowires of the transistor structure is a plurality of merged vertical arrangements of horizontal silicon nanowires.

3. The integrated circuit structure of claim 1 , wherein the plurality of merged vertical arrangements of horizontal nanowires and the plurality of gate stacks of the transistor structure are on an insulating layer on the semiconductor substrate.

4. The integrated circuit structure of claim 1 , wherein individual ones of the plurality of merged vertical arrangements of horizontal nanowires of the transistor structure are merged by epitaxial semiconductor structures.

5. The integrated circuit structure of claim 1 , wherein the semiconductor island comprises a first NWell region, and the varactor structure and the tap structure are over the first NWell region of the semiconductor island, and wherein the semiconductor substrate comprises a second NWell region, and the transistor structure is over the second NWell region.

6. The integrated circuit structure of claim 1 , wherein each of the plurality of discrete gate stacks of the varactor structure comprises a high-k gate dielectric layer and a metal gate electrode, wherein each of the plurality of merged gate stacks of the tap structure comprises a high-k gate dielectric layer and a metal gate electrode, and wherein each of the plurality of gate stacks of the transistor structure comprises a high-k gate dielectric layer and a metal gate electrode.

7. A computing device, comprising:
a board; and
a component coupled to the board, the component including an integrated circuit structure, comprising:
a varactor structure on a semiconductor island on a semiconductor substrate, the varactor structure comprising a plurality of discrete gate stacks on the semiconductor island;
a tap structure adjacent to the varactor structure on the semiconductor island, the tap structure comprising a plurality of merged gate stacks on the semiconductor island; and
a transistor structure on the semiconductor substrate, the transistor structure isolated from the semiconductor island, and the transistor structure comprising a plurality of merged vertical arrangements of horizontal nanowires, and a plurality of gate stacks over and surrounding corresponding ones of the plurality of merged vertical arrangements of horizontal nanowires.

8. The computing device of claim 7 , further comprising:
a memory coupled to the board.

9. The computing device of claim 7 , further comprising:
a communication chip coupled to the board.

10. The computing device of claim 7 , wherein the component is a packaged integrated circuit die.

11. A method of fabricating an integrated circuit structure, the method comprising:
forming a varactor structure on a semiconductor island on a semiconductor substrate, the varactor structure comprising a plurality of discrete gate stacks on the semiconductor island;
forming a tap structure adjacent to the varactor structure on the semiconductor island, the tap structure comprising a plurality of merged gate stacks on the semiconductor island; and
forming a transistor structure on the semiconductor substrate, the transistor structure isolated from the semiconductor island, and the transistor structure comprising a plurality of merged vertical arrangements of horizontal nanowires, and a plurality of gate stacks over and surrounding corresponding ones of the plurality of merged vertical arrangements of horizontal nanowires.

12. The method of claim 11 , wherein the plurality of merged vertical arrangements of horizontal nanowires of the transistor structure is a plurality of merged vertical arrangements of horizontal silicon nanowires.

13. The method of claim 11 , wherein the plurality of merged vertical arrangements of horizontal nanowires and the plurality of gate stacks of the transistor structure are on an insulating layer on the semiconductor substrate.

14. The method of claim 11 , wherein individual ones of the plurality of merged vertical arrangements of horizontal nanowires of the transistor structure are merged by epitaxial semiconductor structures.

15. The method of claim 11 , wherein the semiconductor island comprises a first NWell region, and the varactor structure and the tap structure are over the first NWell region of the semiconductor island, and wherein the semiconductor substrate comprises a second NWell region, and the transistor structure is over the second NWell region.

16. The method of claim 11 , wherein each of the plurality of discrete gate stacks of the varactor structure comprises a high-k gate dielectric layer and a metal gate electrode, wherein each of the plurality of merged gate stacks of the tap structure comprises a high-k gate dielectric layer and a metal gate electrode, and wherein each of the plurality of gate stacks of the transistor structure comprises a high-k gate dielectric layer and a metal gate electrode.

17. A method of fabricating a computing device, the method comprising:
providing a board; and
coupling a component to the board, the component including an integrated circuit structure, comprising:
a varactor structure on a semiconductor island on a semiconductor substrate, the varactor structure comprising a plurality of discrete gate stacks on the semiconductor island;
a tap structure adjacent to the varactor structure on the semiconductor island, the tap structure comprising a plurality of merged gate stacks on the semiconductor island; and
a transistor structure on the semiconductor substrate, the transistor structure isolated from the semiconductor island, and the transistor structure comprising a plurality of merged vertical arrangements of horizontal nanowires, and a plurality of gate stacks over and surrounding corresponding ones of the plurality of merged vertical arrangements of horizontal nanowires.

18. The method of claim 17 , further comprising:
coupling a memory to the board.

19. The method of claim 17 , further comprising:
coupling a communication chip to the board.

20. The method of claim 17 , wherein the component is a packaged integrated circuit die.

Assignees

• Intel Corp

Inventors

• Kar Ayan
• Morarka Saurabh
• Nieva-Lozano Carlos
• Kolluru Kalyan
• Guha Biswajeet
• Lin Chung-Hsun
• Greene Brian
• Ghani Tahir

Classifications

• H10P14/3462

  Nanowires · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10D62/121

  oriented parallel to substrates · CPC title

• H10D1/045

  of capacitors having potential barriers, e.g. varactors · CPC title

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title