Bottom source trench MOSFET with shield electrode

Patent metadata

Field	Value
Publication number	US-11869967-B2
Application number	US-202117401183-A
Country	US
Kind code	B2
Filing date	Aug 12, 2021
Priority date	Aug 12, 2021
Publication date	Jan 9, 2024
Grant date	Jan 9, 2024

Abstract

An improved inverted field-effect-transistor semiconductor device and method of making thereof may comprise a source layer on a bottom and a drain disposed on a top of a semiconductor substrate and a vertical current conducting channel between the source layer and the drain controlled by a trench gate electrode disposed in a gate trench lined with an insulating material. A heavily doped drain region is disposed near the top of the substrate surrounding an upper portion of a shield trench and the gate trench. A doped body contact region is disposed in the substrate and surrounding a lower portion of the shield trench. A shield electrode extends upward from the source layer in the shield trench for electrically shorting the source layer and the body region wherein the shield structure extends upward to a heavily doped drain region and is insulated from the heavily doped drain region to act as a shield electrode.

First claim

What is claimed is:

1. An inverted field-effect-transistor (iT-FET) semiconductor device, comprising a source layer on a bottom and a drain metal disposed on a top of a semiconductor substrate:
a vertical current conducting channel between said source layer and said drain metal controlled by a trench gate electrode disposed in a gate trench lined with an insulating material;
a heavily doped drain region disposed near the top of the substrate surrounding an upper portion of a shield trench and the gate trench;
a doped body region disposed in the substrate and surrounding a lower portion of the shield trench;
a shield electrode extending upward from the source layer in the shield trench electrically shorting the source layer and the body region, wherein the shield electrode extends upward to the heavily doped drain region and is insulated from the heavily doped drain region.

2. The iT-FET semiconductor device of claim 1 , wherein the shield structure further comprises a conductive plug extending upward from the source layer in the shield trench through the body region to at least part of the drift region.

3. The iT-FET semiconductor device of claim 1 , wherein the shield electrode further comprises a tungsten plug extending upward from the source layer in the shield trench.

4. The iT-FET semiconductor device of claim 1 , wherein the shield electrode further comprises a titanium silicide plug extending upward from the source in the shield trench.

5. The iT-FET semiconductor device of claim 1 , wherein the source layer of the semi-conductor substrate is heavily doped with impurity of a first conductivity type and the semi-conductor substrate further comprises an epitaxial layer formed on top of the source layer, doped with impurity of a second conductivity type, wherein the second conductivity type is opposite of the first conductivity type.

6. The iT-FET semiconductor device of claim 5 , wherein the body region is formed in the epitaxial layer and is heavily doped with impurities of the second conductivity type.

7. The iT-FET semiconductor device of claim 5 , wherein the heavily doped drain region is formed in the epitaxial layer and is heavily doped with ions of the first conductivity type.

8. The iT-FET semiconductor device of claim 7 , wherein an insulator layer between the shield electrode and the heavily doped drain region and the drift region is thicker than portions of the insulating material between the gate electrode and the source layer and body region.

9. The iT-FET semiconductor device of claim 7 , further comprising a drift region between the body region and the heavily doped drain region formed in the epitaxial layer wherein the drift region is less heavily doped with impurity of the first conductivity type than the heavily doped drain region.

10. The iT-FET semiconductor device of claim 9 , wherein the drift region has an impurity concentration gradient wherein the impurity concentration is highest near the heavily doped drain region and the impurity concentration gradient decreases deeper into the epitaxial layer below the heavily doped drain region.

11. The iT-FET semiconductor device of claim 1 , further comprising a conductive drain contact plug in contact with the heavily doped drain region and the drain metal.

12. A method of making an iT-FET semi-conductor device comprising:
a) forming an epitaxial layer doped with impurities of a second conductivity type on a substrate heavily doped with impurities of a first conductivity type wherein the first conductivity type is opposite of the second conductivity type, wherein the substrate acts as a source layer;
b) forming a gate trench through the epitaxial layer and into the source layer;
c) lining the gate trench with an insulating material and forming a gate electrode in the gate trench;
d) forming a heavily doped drain region doped with impurities of the first conductivity type in the epitaxial layer;
d′) forming a drift region doped with impurities of first conductivity type in the epitaxial layer below the heavily doped drain region;
e) forming a shield trench in the epitaxial layer through the heavily doped drain region, and drift region;
f) heavily doping a body contact region with impurities of the second conductivity type at the bottom of the shield trench;
g) lining the shield trench with an insulating material;
h) deepening the shield trench into the source layer through the body contact region and forming a shield structure in the shield trench wherein the shield structure extends upward from the source layer in the shield trench electrically shorting the source region and the body region and wherein the shield structure extends upward into a heavily doped drain region and is insulated from the drain contact region to act as a shield electrode;
i) forming a drain on top of the epitaxial layer.

13. The method of making an iT-FET semiconductor device of claim 12 , wherein the shield electrode extends from a bottom of the drain through the shield trench and body region to the source.

14. The method of making an iT-FET semiconductor device of claim 12 , wherein forming the shield electrode further comprises forming a conductive plug extending upward from the source in the shield trench through the body region to at least part of the drift region.

15. The method of making an iT-FET semiconductor device of claim 14 , wherein the conductive plug is a tungsten plug extending upward from the source in the shield trench.

16. The method of making an iT-FET semiconductor device of claim 14 , wherein the conductive plug is lined with titanium silicide extending upward from the source in the shield trench.

17. The method of making an iT-FET semiconductor device of claim 12 , wherein d) further comprises forming a drift region between the body region and the drain contact region formed in the epitaxial layer wherein the drift region is more lightly doped with impurity of the first conductivity type than the heavily doped drain region.

18. The method of making an iT-FET semiconductor device of claim 17 , wherein forming the drift region further comprises forming an impurity concentration gradient in the drift region wherein the impurity concentration is highest near the drain contact region and the ion concentration gradient decreases deeper into the epitaxial layer below the heavily doped drain region.

19. The method of making an iT-FET semiconductor device of claim 12 , wherein h) further comprises lining the side walls of the shield trench with a shield insulator thicker than the insulation material in the gate trench.

20. The method of making an iT-FET semiconductor device of claim 12 , wherein forming a drain on top of the epitaxial layer further comprises forming conductive drain contact plug in contact with the heavily doped drain region and a drain metal over top the drain contact plug.

Assignees

• Alpha & Omega Semiconductor Int Lp

Inventors

• Lui Sik
• Bobde Madhur
• Guan Lingpeng
• Zhang Lei

Classifications

• H10D64/117

  Recessed field plates, e.g. trench field plates or buried field plates · CPC title

• H10D64/01

  Manufacture or treatment · CPC title

• H10D62/393

  Body regions of DMOS transistors or IGBTs  (cell layout of DMOS H10D62/127) · CPC title

• H10D30/668

  having trench gate electrodes, e.g. UMOS transistors · CPC title

• H10D30/0297

  using recessing of the gate electrodes, e.g. to form trench gate electrodes · CPC title