Semiconductor device with a vertical channel formed through a plurality of semiconductor layers

Patent metadata

Field	Value
Publication number	US-9406793-B2
Application number	US-201414529959-A
Country	US
Kind code	B2
Filing date	Oct 31, 2014
Priority date	Jul 3, 2014
Publication date	Aug 2, 2016
Grant date	Aug 2, 2016

Abstract

Semiconductor devices and manufacturing methods are provided for making channel and gate lengths independent from lithography. Also, semiconductor devices and manufacturing methods are provided for increasing resistivity between drain and channel to allow for higher voltage operation. For example, a semiconductor device includes a first doped layer implanted in a semiconductor substrate forming one of a source or a drain and a gate metal layer disposed over the first doped layer. The semiconductor device further includes a second doped layer disposed over the gate metal forming the other the source or the drain, where the first doped layer, the gate metal layer and the second doped layer form a vertical stack of layers of the semiconductor device. The semiconductor device further includes a conduction channel formed in a trench that extends vertically through the vertical stack of layers and terminates at the semiconductor substrate.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a first doped layer implanted in a semiconductor substrate forming one of a source or a drain;
a gate metal layer disposed over the first doped layer;
a second doped layer disposed over the gate metal layer forming the other of the source or the drain, wherein the first doped layer, the gate metal layer and the second doped layer form a vertical stack of layers of the semiconductor device; and
a conduction channel formed in a trench that extends vertically through the first doped layer, the gate metal layer and the second doped layer of the vertical stack of layers and terminates at the semiconductor substrate.

2. The semiconductor device of claim 1 , further comprising:
a metal gate work-function formed over a portion of the gate metal layer inside the trench; and
a high-k dielectric grown over the metal gate work-function inside the trench.

3. The semiconductor device of claim 1 , further comprising:
a first dielectric layer arranged between the first doped layer and the gate metal layer; and
a hard mask and a second dielectric layer arranged between the gate metal layer and the second doped layer, the hard mask disposed over the gate metal layer and the second dielectric layer arranged between the hard mask and the second doped layer.

4. The semiconductor device of claim 1 , further comprising:
a first contact coupled to the first doped layer;
a gate contact coupled to the gate metal layer; and
a second contact coupled to the second doped layer.

5. The semiconductor device of claim 1 , further comprising:
a first extension grown inside the trench from the first doped layer to a bottom portion of the gate metal layer that is inside the trench; and
a second extension grown inside the trench from the second doped layer to a top portion of the gate metal layer inside the trench.

6. The semiconductor device of claim 1 , wherein the conduction channel formed in the trench extends beyond the trench to cover a portion of the second doped layer to form an extended electrical connection layer disposed over the second doped layer.

7. The semiconductor device of claim 6 , further comprising:
an isolation layer formed over the extended electrical connection.

8. The semiconductor device of claim 1 , wherein the conduction channel formed in the trench terminates at a top surface of the second doped layer.

9. The semiconductor device of claim 1 , wherein the gate metal layer is deposited using atomic layer deposition.

10. The semiconductor device of claim 1 , wherein the conduction channel includes a silicon material that is doped relatively lightly with respect to the first and second doped layers.

11. The semiconductor device of claim 1 , wherein the conduction channel is doped with a material different from doping of the first and second doped layers.

12. A semiconductor device, comprising:
a first doped layer implanted in a semiconductor substrate forming one of a source or a drain;
a first dielectric layer disposed over the first doped layer;
a gate metal layer disposed over the first dielectric layer;
a second dielectric layer disposed over the gate metal layer;
a second doped layer disposed over the second dielectric layer forming the other of the source or the drain, wherein the first doped layer, the first dielectric layer, the gate metal layer, the second dielectric layer, and the second doped layer form a vertical stack of layers of the semiconductor device; and
a conduction channel formed in a trench that extends vertically through the first doped layer, the first dielectric layer, the gate metal layer, the second dielectric layer, and the second doped layer of the vertical stack of layers, wherein a width of the conduction channel at the gate metal layer is smaller than a width of the conduction channel at the first dielectric layer underneath the gate metal layer.

13. The semiconductor device of claim 12 , wherein a thickness of the conduction channel at the second dielectric layer is smaller than a thickness of the conduction channel at the first dielectric layer.

14. The semiconductor device of claim 12 , further comprising:
a gate isolation layer arranged between the first dielectric layer and the second dielectric layer, encompassing the gate metal layer.

15. The semiconductor device of claim 12 , wherein the conduction channel is separated from the gate metal layer and the second dielectric layer by a gate oxide.

16. The semiconductor device of claim 12 , wherein a width of the conduction channel at the second dielectric layer is substantially equal to the width of the conduction channel at the gate metal layer and is smaller than the width of the conduction channel at the first dielectric layer.

17. The semiconductor device of claim 16 , further comprising a silicon pad formed on top of the conduction channel and inside the second doped layer.

18. The semiconductor device of claim 17 , wherein a width of the silicon pad is substantially equal to the width of the conduction channel at the first dielectric layer.

19. The semiconductor device of claim 12 , wherein the trench and the conduction channel extend vertically through the first doped layer and terminate at the semiconductor substrate.

20. The semiconductor device of claim 12 , wherein the semiconductor device is a laterally diffused metal oxide semiconductor (LDMOS) and the conduction channel at the first dielectric layer increases resistance to allow higher voltage operation of the LDMOS.

Assignees

• Broadcom Corp

Inventors

• Zhao Sam Ziqun
• Hui Frank

Classifications

• H10D62/292

  Non-planar channels of IGFETs (resulting from the gate electrode dispositions, e.g. within trenches H10D64/512) · CPC title

• H10D62/235

  of IGFETs (IGFETs having buried channels H10D30/637) · CPC title

• H10D62/149

  Source or drain regions of field-effect devices · CPC title

• H10D62/116

  adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions · CPC title

• H10D30/664

  Inverted VDMOS transistors, i.e. source-down VDMOS transistors · CPC title