Scalable cache coherency protocol

US11544193B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11544193-B2
Application numberUS-202117315725-A
CountryUS
Kind codeB2
Filing dateMay 10, 2021
Priority dateSep 11, 2020
Publication dateJan 3, 2023
Grant dateJan 3, 2023

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

A scalable cache coherency protocol for system including a plurality of coherent agents coupled to one or more memory controllers is described. The memory controller may implement a precise directory for cache blocks from the memory to which the memory controller is coupled. Multiple requests to a cache block may be outstanding, and snoops and completions for requests may include an expected cache state at the receiving agent, as indicated by a directory in the memory controller when the request was processed, to allow the receiving agent to detect race conditions. In an embodiment, the cache states may include a primary shared and a secondary shared state. The primary shared state may apply to a coherent agent that bears responsibility for transmitting a copy of the cache block to a requesting agent. In an embodiment, at least two types of snoops may be supported: snoop forward and snoop back.

First claim

Opening claim text (preview).

What is claimed is: 1. A system comprising: a plurality of coherent agents, wherein a given agent of the plurality of coherent agent comprises one or more caches to cache memory data; a memory controller coupled to one or more memory devices, wherein the memory controller includes a directory configured to track which of the plurality of coherent agents is caching copies of a plurality of cache blocks in the memory devices and states of the cached copies in the plurality of coherent agents; wherein, based on a first request for a first cache block by a first agent of the plurality of coherent agents, the memory controller is configured to: read an entry corresponding to the first cache block from the directory, issue a snoop to a second agent of the plurality of coherent agents that has a cached copy of the first cache block according to the entry, and include an identifier of a first state of the first cache block in the second agent in the snoop; and wherein, based on the snoop, the second agent is configured to: compare the first state to a second state of the first cache block in the second agent, and delay processing of the snoop based on the first state not matching the second state until the second state is changed to the first state in response to a different communication related to a different request than the first request. 2. The system as recited in claim 1 , wherein the memory controller is configured to: determine a completion count indicating a number of completions that the first agent will receive for the first request, wherein the determination is based on the states from the entry, include the completion count in a plurality of snoops issued based on the first request including the snoop issued to the second agent; and wherein the first agent is configured to: initialize a completion counter with the completion count based on receiving an initial completion from one of the plurality of coherent agents, update the completion counter based on receiving a subsequent completion from another one of the plurality of coherent agents, and complete first request based on the completion counter. 3. The system as recited in claim 1 wherein the memory controller is configured to update the states in the entry of the directory to reflect completion of the first request based on issuing a plurality of snoops based on the first request. 4. The system as recited in claim 1 wherein the first agent is configured to detect a second snoop received by the first agent to the first cache block, wherein the first agent is configured to absorb the second snoop into the first request. 5. The system as recited in claim 4 wherein the first agent is configured to process the second snoop subsequent to completing the first request. 6. The system as recited in claim 5 wherein the first agent is configured to forward the first cache block to a third agent indicated in the second snoop subsequent to completing the first request. 7. The system as recited in claim 1 wherein: a third agent is configured to generate a conditional change to exclusive state request based on a store conditional instruction to a second cache block that is in a valid state at the third agent, and the memory controller is configured to determine if the third agent retains a valid copy of the second cache block based on a second entry in the directory associated with the second cache block, and the memory controller is configured to transmit a completion indicating failure to the third agent and terminate the conditional change to exclusive request based on a determination that the third agent no longer retains the valid copy of the second cache block. 8. The system as recited in claim 7 wherein the memory controller is configured to issue one or more snoops to other ones of the plurality of coherent agents as indicated by the second entry based on a determination that the third agent retains the valid copy of the second cache block. 9. The system as recited in claim 1 wherein the snoop indicates that the second agent is to transmit the first cache block to the first agent based on the first state being primary shared, and wherein the snoop indicates that the second agent is not to transmit the first cache block based on the first state being secondary shared. 10. The system as recited in claim 9 wherein the snoop indicates that the second agent is to transmit the first cache block even in the event that the first state is secondary shared. 11. The system as recited in claim 1 wherein the snoop comprises a message transmitted specifically to the second agent. 12. A coherent agent comprising: one or more caches to cache memory data; and a control circuit coupled to the one or more caches, wherein: the control circuit is configured to receive a snoop from a memory controller when the one or more caches has a cached copy of a first cache block that has been requested by a different coherent agent in a first request transmitted to the memory controller by the different coherent agent, the snoop includes an identifier of a first state in the one or more caches according to a directory in the memory controller, the control circuit is configured to compare the first state of the first cache block to a second state of the first cache block in the one or more caches, and the control circuit is configured to delay processing of the snoop based on the first state not matching the second state until the second state is changed to the first state in response to a different communication related to a different request than the first request. 13. A method, in a system including a plurality of coherent agents, wherein a given agent of the plurality of coherent agent comprises one or more caches to cache memory data, and a memory controller coupled to one or more memory devices, wherein the memory controller includes a directory configured to track which of the plurality of coherent agents is caching copies of a plurality of cache blocks in the memory devices and states of the cached copies in the plurality of coherent agents, the method comprising: based on a first request for a first cache block by a first agent of the plurality of coherent agents: reading, by the memory controller, an entry corresponding to the first cache block from the directory; issuing, by the memory controller, a snoop to a second agent of the plurality of coherent agents that has a cached copy of the first cache block according to the entry; and including, by the memory controller, an identifier of a first state of the first cache block in the second agent in the snoop; and based on the snoop: comparing, by the second agent, the first state to a second state of the first cache block in the second agent, and delaying, by the second agent, the processing of the snoop based on the first state not matching the second state until the second state is changed to the first state in response to a different communication related to a different request than the first request. 14. The method as recited in claim 13 , further comprising: determining, by the memory controller, a completion count indicating a number of completions that the first agent will receive for the first request, wherein the determination is based on the states from the entry; including, by the memory controller, the completion count in a plurality of snoops issued based on the first request including the snoop issued to the second agent; initializing, by the first agent, a completion counter with the completion count based on receiving an initial completion from one of the plurality of coherent agents;

Assignees

Inventors

Classifications

  • Cache consistency protocols · CPC title

  • using a bus scheme, e.g. with bus monitoring or watching means · CPC title

  • Distributed directories, e.g. linked lists of caches · CPC title

  • Latency reduction · CPC title

  • Reliability improvement, data loss prevention, degraded operation etc · CPC title

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US11544193B2 cover?
A scalable cache coherency protocol for system including a plurality of coherent agents coupled to one or more memory controllers is described. The memory controller may implement a precise directory for cache blocks from the memory to which the memory controller is coupled. Multiple requests to a cache block may be outstanding, and snoops and completions for requests may include an expected ca…
Who is the assignee on this patent?
Apple Inc
What technology area does this patent fall under?
Primary CPC classification G06F12/0815. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Jan 03 2023 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).