Display device including a node connection line, a shielding portion and driving voltage line

Patent metadata

Field	Value
Publication number	US-11864417-B2
Application number	US-202217680563-A
Country	US
Kind code	B2
Filing date	Feb 25, 2022
Priority date	Jun 15, 2016
Publication date	Jan 2, 2024
Grant date	Jan 2, 2024

Abstract

A display device includes a scan line extending in a first direction, a data line and a driving voltage line extending in a second direction crossing the first direction, a switching thin film transistor (“TFT”) connected to the scan line and the data line, a driving TFT connected to the switching TFT and including a driving semiconductor layer and a driving gate electrode, a storage capacitor connected to the driving TFT and including first and second storage capacitor plates, a node connection line between the data line and the driving voltage line and connected to the driving gate electrode, and a shielding portion between the data line and the node connection line.

First claim

What is claimed is:

1. A display device comprising:
a first scan line extending in a first direction;
a data line extending in a second direction crossing the first direction;
a first transistor comprising a first semiconductor layer and a first gate electrode, wherein the first semiconductor layer is electrically connected to the data line via a first contact hole;
a second transistor electrically connected to the first transistor, the second transistor comprising a second semiconductor layer and a second gate electrode;
a third transistor comprising a third semiconductor layer and a third gate electrode;
a node connection line, wherein a first portion of the node connection line is electrically connected to the third semiconductor layer via a second contact hole, and a second portion of the node connection line is electrically connected to the second gate electrode via a third contact hole;
a shielding portion, wherein an end portion of the shielding portion disposed between the first contact hole and the second contact hole in a plan view; and
a driving voltage line extending in the second direction, wherein a portion of the driving voltage line overlaps a portion of the third semiconductor layer.

2. The display device of claim 1 , wherein:
the third gate electrode comprises a first sub-gate electrode and a second sub-gate electrode,
the third semiconductor layer comprises a first sub-channel region and a second sub-channel region, and
the portion of the driving voltage line overlaps the portion of the third semiconductor layer which is disposed between the first sub-channel region and the second sub-channel region.

3. The display device of claim 2 , wherein the first scan line comprises the first gate electrode, the first sub-gate electrode and the second sub-gate electrode.

4. The display device of claim 1 , wherein the shielding portion comprises a metal layer.

5. The display device of claim 1 , wherein the shielding portion has a constant voltage level.

6. The display device of claim 1 , wherein the first semiconductor layer and the second semiconductor layer are integrally coupled to each other, and the second semiconductor layer and the third semiconductor layer are integrally coupled to each other.

7. The display device of claim 1 , wherein the node connection line is between the data line and the driving voltage line in a plan view.

8. A display device comprising:
a first scan line extending in a first direction;
a data line extending in a second direction crossing the first direction;
a first transistor comprising a first semiconductor layer that comprises a first channel region overlapped by a first portion of the first scan line, wherein the first semiconductor layer is electrically connected to the data line via a first contact hole;
a second transistor electrically connected to the first transistor, the second transistor comprising a second semiconductor layer having a curved shape in a plan view and a second gate electrode;
a third transistor comprising a third semiconductor layer that comprises a first sub-channel region and a second sub-channel region, wherein the first sub-channel region and the second sub-channel region are overlapped by a second portion and a third portion of the first scan line, respectively;
a driving voltage line extending in the second direction, wherein a portion of the driving voltage line overlaps a portion of the third semiconductor layer,
a node connection line between the data line and the driving voltage line in a plan view.

9. The display device of claim 8 , wherein the portion of the driving voltage line overlaps the portion of the third semiconductor layer which is disposed between the first sub-channel region and the second sub-channel region.

10. The display device of claim 8 , further comprising:
a shielding portion, an end portion of the shielding portion is between the data line and the driving voltage line in a plan view.

11. The display device of claim 10 , wherein a first portion of the node connection line is electrically connected to the third semiconductor layer via a second contact hole, and a second portion of the node connection line is electrically connected to the second gate electrode via a third contact hole.

12. The display device of claim 11 , wherein the end portion of the shielding portion disposed on a virtual line connecting the first contact hole and the second contact hole in a plan view.

13. The display device of claim 10 , wherein the shielding portion comprises a metal layer.

14. The display device of claim 10 , wherein the shielding portion has a constant voltage level.

15. The display device of claim 8 , wherein the first semiconductor layer and the second semiconductor layer are integrally coupled each other, and the second semiconductor layer and the third semiconductor layer are integrally coupled each other.

16. A display device comprising:
a first scan line extending in a first direction;
a data line extending in a second direction crossing the first direction;
a first transistor electrically connected to the first scan line and the data line, wherein a first semiconductor layer of the first transistor is electrically connected to the data line via a first contact hole;
a second transistor electrically connected to the first transistor, the second transistor comprising a second semiconductor layer and a second gate electrode;
a third transistor electrically connected to the first scan line;
a driving voltage line extending in the second direction, wherein a portion of the driving voltage line overlaps a portion of a third semiconductor layer of the third transistor;
a node connection line electrically connecting the second gate electrode and the third semiconductor layer of the third transistor; and
a shielding portion, wherein an end portion of the shielding portion disposed between the data line and the driving voltage line in a plan view.

17. The display device of claim 16 , wherein the third semiconductor layer comprises a first sub-channel region and a second sub-channel region,
wherein the first sub-channel region and the second sub-channel region are overlapped by two portions of the first scan line, respectively, and
wherein the portion of the third semiconductor layer overlapped by the portion of the driving voltage line is a portion between the first sub-channel region and the second sub-channel region.

18. The display device of claim 16 , wherein a first portion of the node connection line is electrically connected to the third semiconductor layer via a second contact hole, and a second portion of the node connection line is electrically connected to the second gate electrode via a third contact hole, and
wherein the end portion of the shielding portion disposed on a virtual line connecting the first contact hole and the second contact hole in a plan view.

19. The display device of claim 16 , wherein the shielding portion comprises a metal layer.

20. The display device of claim 16 , wherein the shielding portion has a constant voltage level.

Assignees

• Samsung Display Co Ltd

Inventors

• Choi Junwon
• In Yunkyeong
• Hwang Wonmi
• An Junyong

Classifications

• H10K59/00 Primary

  Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00 · CPC title

• G09G3/3233 Primary

  with pixel circuitry controlling the current through the light-emitting element · CPC title

• H10D86/481

  integrated with passive devices, e.g. auxiliary capacitors · CPC title

• H10D86/60

  wherein the TFTs are in active matrices · CPC title

• H10K59/123

  Connection of the pixel electrodes to the thin film transistors [TFT] · CPC title