Multi mode memory module with data handlers

Patent metadata

Field	Value
Publication number	US-11862267-B2
Application number	US-201916286246-A
Country	US
Kind code	B2
Filing date	Feb 26, 2019
Priority date	Apr 14, 2008
Publication date	Jan 2, 2024
Grant date	Jan 2, 2024

Abstract

A memory module is operable in a computer system to communicate data with a system memory controller via a system memory bus. The memory module comprises a plurality of memory devices mounted on a circuit board, a data module mounted on the circuit board and coupled between the plurality of memory devices and the system memory bus, and a control circuit mounted on the circuit board and coupled to the data module, the plurality of memory devices, and the system memory bus. The data module includes a plurality of data handlers in a plurality of integrated circuits. The memory module is operable in any of a plurality of modes, including a first mode and a second mode. The plurality of memory devices in the first mode is accessed by the system memory controller for normal memory read or write operations. The plurality of memory devices in the second mode communicate data signals with the data module while the memory module is not being accessed by the system memory controller for normal memory read or write operations.

First claim

We claim:

1. A memory module operable in a computer system including a system memory controller coupled to a system memory bus having a bit width N, where N is a positive integer, the memory module comprising:
a printed circuit board (PCB) including a connector that fits into a corresponding slot connector of the computer system whereby the memory module is operatively coupled to the system memory controller of the computer system via the system memory bus;
memory devices mounted on the PCB and organized in one or more N-bit-wide ranks, the memory devices having address and control ports and data ports;
a data module coupled to the data ports of the memory devices and to the connector, the data module including a plurality of data handlers in respective physically separate integrated circuit packages mounted on respective portions of the PCB and coupled to respective n-bit-wide segments of the memory devices, where n is a positive integer smaller than N; and
a control circuit mounted on the PCB and coupled to the connector, the data module, and address and control ports of the memory devices;
wherein, during a normal memory read or write operation, the control circuit is configurable to receive system address and control signals from the system memory controller via the connector and to output registered memory address and control signals for the normal memory read or write operation, and each respective data handler of the data module is configurable to propagate respective read or write data signals associated with the normal memory read or write operation between a respective n-bit-wide segment of the memory devices and a respective n-bit-wide segment of the system memory bus, the respective read or write data signals being output or received by at least one memory device in the respective n-bit-wide segment of the memory devices in response to the registered memory address and control signals; and
wherein, during testing of the memory module, the control circuit is configurable to output test address and control signals, the each respective data handler of the data module is configurable to isolate respective data paths from the memory controller to the respective n-bit-wide segment of the memory devices and to output respective test data signals to the respective segment of the memory devices based on information received from the control circuit, and the respective test data signals including test data to be received by and written into one or more memory devices in the respective segment of the memory devices in response to the test address and control signals from the control circuit.

2. The memory module of claim 1 , wherein, during testing of the memory module:
the control circuit is configurable to output verification address and control signals;
the one or more memory devices are configurable to output respective verification data signals in response to the verification address and control signals; and
the each respective data handler of the data module is configurable to receive the respective verification data signals, to compare respective verification data in the respective verification data signals with expected data, and to output comparison results.

3. The memory module of claim 2 , wherein the expected data are stored in the each respective data handler.

4. The memory module of claim 2 , wherein n=8 and N=64 or 72.

5. The memory module of claim 2 , wherein the memory devices are dynamic random access memory devices, wherein each memory device is 8-bit-wide, and wherein the at least one memory device includes one respective memory device in one of the one or more ranks.

6. The memory module of claim 2 , wherein the memory devices are dynamic random access memory devices, wherein each memory device is 4-bit-wide, and wherein the at least one memory device includes two respective memory devices in one of the one or more ranks.

7. The memory module of claim 2 , wherein the each respective data handler of the data module is configurable to generate the respective test data signals with programmable slew rates and programmable peak values so that characteristics of the respective test data signals correspond to characteristics of write data signals from the memory controller.

8. The memory module of claim 2 , wherein the memory module is operable at an operational speed according to a system clock, wherein the at least one respective memory device is configurable to output or receive the respective data signals at the operational speed in response to the registered memory address and control signals, and wherein the each respective data handler is configurable to output the respective test data signals at the operational speed in response to a write command from the control circuit.

9. The memory module of claim 1 , wherein the data module includes first and second data handlers in first and second integrated circuit packages, respectively, wherein, during the normal memory read or write operation, the first integrated circuit package is configurable to propagate first data signals between a first n-bit-wide portion of the memory devices and a first n-bit-wide segment of the system memory bus, and the second integrated circuit package is configurable to propagate second data signals between a second n-bit-wide portion of the memory devices and a second n-bit-wide segment of the system memory bus independently of and concurrently with the first integrated circuit package propagating the first data signals.

10. The memory module of claim 9 , wherein during testing of the memory module, the first integrated circuit package is configurable to write first test data into at least one first memory device by outputting first test data signals, and the second integrated circuit package is configurable to write second test data into at least one second memory device by outputting second test data signals independently of and concurrently with the first integrated circuit package outputting the first test data signals.

11. A method, comprising:
at a memory module operable in a computer system including a system memory controller coupled to a system memory bus having a bit width N, the memory module including: a printed circuit board (PCB) including a connector that fits into a corresponding slot connector of the computer system whereby the memory module is operatively coupled to the system memory controller of the computer system via the system memory bus; memory devices mounted on the PCB and organized in one or more N-bit-wide ranks, where N is a positive integer, the memory devices having address and control ports and data ports; a data module coupled to the data ports of the memory devices and to the connector, the data module including a plurality of data handlers in respective physically separate integrated circuit packages mounted on respective portions of the PCB and coupled to respective n-bit-wide segments of the memory devices, where n is a positive integer smaller than N; and a control circuit mounted on the PCB and coupled to the connector, the data module, and address and control ports of the memory devices;
performing normal memory read or write operations, including: receiving, at the control circuit, system address and control signals from the system memory controller via the connector; outputting, from the control circuit, registered memory address and control signals for the normal memory read or write operation; propagating, by each respective data handler of the data module, respective read data signals or respective write data signals associated with the normal memory read or write operation between a respective n-bit-wide segment of the memory devices and a respective n-bit-wide se

Assignees

• Netlist Inc

Inventors

• Lee Hyun
• Bhakta Jayesh R
• Choi Soonju

Classifications

• G11C29/10 Primary

  Test algorithms, e.g. memory scan [MScan] algorithms; Test patterns, e.g. checkerboard patterns · CPC title

• G11C29/12 Primary

  Built-in arrangements for testing, e.g. built-in self testing [BIST] {or interconnection details} · CPC title

• G11C5/04

  Supports for storage elements {, e.g. memory modules}; Mounting or fixing of storage elements on such supports · CPC title