Memory module with data buffering

Patent metadata

Field	Value
Publication number	US-10489314-B2
Application number	US-201715857519-A
Country	US
Kind code	B2
Filing date	Dec 28, 2017
Priority date	Mar 5, 2004
Publication date	Nov 26, 2019
Grant date	Nov 26, 2019

Abstract

A memory module operable to communicate data with a memory controller via a data bus comprises a plurality of memory integrated circuits including first memory integrated circuits and second memory integrated circuits, a data buffer coupled between the first memory integrated circuits and the data bus, and between the second memory integrated circuits and the data bus, and logic coupled to the data buffer. The logic is configured to respond to a first memory command by providing first control signals to the data buffer to enable communication of at least one first data signal between the first memory integrated circuits and the memory controller through the data buffer, and is further configured to respond to a second memory command by providing second control signals to the data buffer to enable communication of at least one second data signal between the second memory integrated circuit and the memory controller through the data buffer.

First claim

We claim:

1. A memory module operable in a computer system to communicate data with a memory controller of the computer system at a specified data rate via a N-bit wide data bus in response to memory commands received from the memory controller, the memory commands including a first memory command and a subsequent second memory command, the first memory command to cause the memory module to receive or output a first burst of N-bit wide data signals and a first burst of data strobes and the second memory command to cause the memory module to receive or output a second burst of N-bit wide data signals and a second burst of data strobes, the memory module comprising:
a printed circuit board having a plurality of edge connections configured to be electrically coupled to a corresponding plurality of contacts of a module slot of the computer system;
a plurality of memory integrated circuits mounted on the printed circuit board and arranged in a plurality of N-bit wide ranks, wherein the plurality of N-bit wide ranks include a first rank configured to receive or output the first burst of N-bit wide data signals and the first burst of data strobes at the specified data rate in response to the first memory command, and a second rank configured to receive or output the second burst of N-bit wide data signals and the second burst of data strobes at the specified data rate in response to the second memory command;
circuitry coupled between the plurality of N-bit wide ranks and the N-bit wide data bus; and
logic coupled to the circuitry and configured to respond to the first memory command by providing first control signals to the circuitry and to subsequently respond to the second memory command by providing second control signals to the circuitry, wherein the circuitry is configured to enable data transfers through the circuitry in response to the first control signals and subsequently in response to the second control signals, wherein respective N-bit wide data signals of the first burst of N-bit wide data signals and respective data strobes of the first burst of data strobes are transferred at the specified data rate between the first rank and the N-bit wide data bus through the circuitry, and wherein respective N-bit wide data signals of the second burst of N-bit wide data signals and respective data strobes of the second burst of data strobes are transferred at the specified data rate between the second rank and the N-bit wide data bus through the circuitry;
wherein the data transfers through the circuitry are registered data transfers enabled in accordance with an overall CAS latency of the memory module, and the circuitry is configured to add a predetermined amount of time delay for each registered data transfer through the circuitry so that the overall CAS latency of the memory module is greater than an actual operational CAS latency of each of the plurality of memory integrated circuits.

2. The memory module of claim 1 , wherein each of the plurality memory integrated circuits has a corresponding load, and wherein the circuitry is configured to isolate the loads of the plurality of memory integrated circuits from the memory controller.

3. The memory module of claim 1 , wherein the logic is coupled to the printed circuit board and is further configured to receive from the memory controller a first set of input address and control signals associated with the first memory command and to respond to the first memory command by outputting a first set of registered address and control signals, and wherein the logic is further configured to subsequently receive from the memory controller a second set of input address and control signals associated with the second memory command and to respond to the second memory command by outputting a second set of registered address and control signals, the first set of input address and control signals including a first set of input chip select signals corresponding to respective ranks of the plurality of ranks and the second set of input address and control signals including a second set of input chip select signals corresponding to respective ranks of the plurality of ranks, the first set of registered address and control signals including a first plurality of registered chip select signals corresponding to respective ones of the first plurality of input chip select signals, the second set of registered address and control signals including a second plurality of registered chip select signals corresponding to respective ones of the second plurality of input chip select signals, the first set of registered chip select signals including a first registered chip select signal having an active signal value and one or more other registered chip select signals each having a non-active signal value, the second set of registered chip select signals including a second registered chip select signal having an active signal value and one or more other registered chip select signals each having a non-active signal value, and wherein the logic is configured to output the first registered chip select signal to the first rank and to output the second registered chip select signal to the second rank.

4. The memory module of claim 1 , further comprising an SPD device that reports the overall CAS latency of the memory module to the memory controller.

5. The memory module of claim 1 , wherein the memory module is configured to receive from the memory controller an on-die-termination (ODT) signal, wherein each of the plurality of memory integrated circuits includes an ODT circuit, the memory module further comprising a termination circuit external to any of the plurality of memory integrated circuits, wherein the termination circuit is configured to receive the ODT signal and is coupled to the ODT circuit of at least one of the plurality of memory integrated circuits, wherein the termination circuit is configured to provide external termination for the at least one of the plurality of memory integrated circuits in response to the ODT signal, and wherein the ODT circuit of the at least one of the plurality of memory integrated circuits is disabled.

6. The memory module of claim 1 , wherein the circuitry includes logic pipelines configured to enable the data transfers through the circuitry in response to the first control signals and subsequently in response to the second control signals.

7. The memory module of claim 1 , wherein the logic is further configured to determine the overall CAS latency of the memory module.

8. The memory module of claim 1 , wherein N is 64 or 72.

9. The memory module of claim 1 , wherein each rank of the plurality of ranks is 72-bits wide, wherein each rank of the plurality of N-bit wide ranks includes 18 4-bit wide memory integrated circuits configured in 9 pairs, wherein a first pair of memory integrated circuits in the first rank is configured to communicate a respective byte of the first burst of N-bit wide data signals in each time interval of a first plurality of time intervals, and wherein a second pair of memory integrated circuits in the second rank is configured to communicate a respective byte of the second burst of N-bit wide data signals in each time interval of a second plurality of time intervals.

10. The memory module of claim 9 , wherein the first pair of memory integrated circuits are configured to simulate an 8-bit wide memory device, and the second pair of memory integrated circuits are configured to simulate another 8-bit wide memory device.

11. The memory module of claim 9 , further comprising an SPD device programmed with data to characterize each pair of memory integrated circuits as a virtual 8-bit wide memory device.

12. The memory module

Assignees

• Netlist Inc

Inventors

• Solomon Jefferey C
• Bhakta Jayesh R

Classifications

• G06F13/4282

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title

• G11C5/04

  Supports for storage elements {, e.g. memory modules}; Mounting or fixing of storage elements on such supports · CPC title

• G06F13/4243

  with synchronous protocol · CPC title

• G11C15/00

  Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores · CPC title

• G11C7/1072

  for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories · CPC title