Semiconductor device

Patent metadata

Field	Value
Publication number	US-11856773-B2
Application number	US-202117176398-A
Country	US
Kind code	B2
Filing date	Feb 16, 2021
Priority date	May 28, 2020
Publication date	Dec 26, 2023
Grant date	Dec 26, 2023

Abstract

A semiconductor device includes a pattern structure; a stack structure including gate and interlayer insulating layers on the pattern structure; and vertical structures penetrating through the stack structure, contacting the pattern structure. The pattern structure includes a lower pattern layer, an intermediate pattern layer, and an upper pattern layer sequentially stacked, the vertical structures including a vertical memory structure penetrating through the upper pattern and intermediate pattern layers and extending into the lower pattern layer, the intermediate pattern layer including a first portion, a second portion extending from the first portion and having a decreased thickness, and a third portion extending from the first portion, having an increased thickness, and contacting the vertical memory structure. The second portion of the intermediate pattern layer has a side surface that is lowered while forming a surface curved from an upper surface of the first portion and that contacts the upper pattern layer.

First claim

What is claimed is:

1. A semiconductor device comprising:
a pattern structure;
a stack structure on the pattern structure, the stack structure including gate layers and interlayer insulating layers alternately stacked in a vertical direction; and
a plurality of vertical structures penetrating through the stack structure in the vertical direction and in contact with the pattern structure,
wherein the pattern structure includes a lower pattern layer, an intermediate pattern layer on the lower pattern layer, and an upper pattern layer on the intermediate pattern layer,
wherein the plurality of vertical structures include a vertical memory structure penetrating through the upper pattern layer and the intermediate pattern layer and extending into the lower pattern layer,
wherein the intermediate pattern layer includes a first portion, a second portion extending from the first portion and having a decreased thickness, and a third portion extending from the first portion, having an increased thickness, and contacting the vertical memory structure, and
wherein the second portion of the intermediate pattern layer has a side surface that is curved convexly from an upper surface of the first portion of the intermediate pattern layer toward the lower pattern layer and that contacts the upper pattern layer.

2. The semiconductor device of claim 1 ,
wherein the vertical memory structure comprises:
a core region;
a channel layer on a side surface and a bottom surface of the core region; and
a data storage structure on an outer surface and a bottom surface of the channel layer,

wherein the data storage structure includes a first dielectric layer, a second dielectric layer, and a data storage layer between the first dielectric layer and the second dielectric layer,
wherein the third portion of the intermediate pattern layer is in contact with the channel layer, and
wherein a maximum width of the second portion of the intermediate pattern layer in a horizontal direction is greater than a thickness of the data storage layer in the horizontal direction, facing the gate layers.

3. The semiconductor device of claim 1 ,
wherein the vertical memory structure comprises:
a core region;
a channel layer on a side surface and a bottom surface of the core region; and
a data storage structure on an outer surface and a bottom surface of the channel layer,

wherein the data storage structure includes a first dielectric layer, a second dielectric layer, and a data storage layer between the first dielectric layer and the second dielectric layer,
wherein the third portion of the intermediate pattern layer is in contact with the channel layer, and
wherein a maximum width of the second portion of the intermediate pattern layer in a horizontal direction is greater than a thickness of the channel layer in the horizontal direction, facing the gate layers.

4. The semiconductor device of claim 1 ,
wherein the intermediate pattern layer further comprises a protruding portion extending between the lower pattern layer and the upper pattern layer from a lower region of the second portion, and
wherein the protruding portion comprises a surface extending at a gentler slope than the side surface of the second portion.

5. The semiconductor device of claim 4 , wherein a bottom surface of the protruding portion is at a lower level than a bottom surface of the first portion.

6. The semiconductor device of claim 1 , wherein in the intermediate pattern layer, the second portion comprises a lower side surface, an upper side surface, and a recessed portion recessed between the upper side surface and the lower side surface toward an interior of the intermediate pattern layer.

7. The semiconductor device of claim 1 ,
wherein the pattern structure further comprises an intermediate structure spaced apart from the intermediate pattern layer, on the lower pattern layer,
wherein the intermediate structure includes a material different from a material of the intermediate pattern layer,
wherein the upper pattern layer includes,
a first upper pattern portion in contact with the lower pattern layer;
a second upper pattern portion in contact with the intermediate structure; and
a third upper pattern portion in contact with the intermediate pattern layer, and

wherein the vertical memory structure is spaced apart from the intermediate structure.

8. The semiconductor device of claim 7 ,
wherein the plurality of vertical structures further comprises:
a vertical support structure penetrating through the upper pattern portion and the intermediate structure and extending into the lower pattern layer; and
a vertical buffer structure penetrating through the first upper pattern portion and extending into the lower pattern layer, and

wherein the vertical buffer structure is spaced apart from the intermediate pattern layer and the intermediate structure.

9. The semiconductor device of claim 1 ,
wherein the intermediate pattern layer includes a first polysilicon layer,
wherein the upper pattern layer includes a second polysilicon layer, and
wherein the upper pattern layer contacts the upper surface of the first portion and the side surface of the second portion.

10. A semiconductor device comprising:
a pattern structure;
a stack structure on the pattern structure, the stack structure including gate layers and interlayer insulating layers alternately stacked in a vertical direction; and
a plurality of vertical structures penetrating through the stack structure in the vertical direction and in contact with the pattern structure,
wherein the pattern structure comprises,
a lower pattern layer;
an upper pattern layer on the lower pattern layer; and
an intermediate structure and an intermediate pattern layer spaced apart from each other and including different materials, the intermediate structure and the intermediate pattern layer being between the lower pattern layer and the upper pattern layer,

wherein the intermediate structure comprises a first intermediate layer and a second intermediate layer,
wherein the first intermediate layer includes:
a lower portion between a lower surface of the second intermediate layer and the lower pattern layer;
an upper portion between an upper surface of the second intermediate layer and the upper pattern layer; and
a side portion between a first side surface of the second intermediate layer and the upper pattern layer,

wherein the second intermediate layer comprises a material different from a material of the first intermediate layer, and
wherein a maximum width of the side portion of the first intermediate layer in a horizontal direction is greater than a thickness of the lower portion of the first intermediate layer in the vertical direction.

11. The semiconductor device of claim 10 , wherein a thickness of the upper portion of the first intermediate layer in the vertical direction is greater than a thickness of the lower portion of the first intermediate layer in the vertical direction.

12. The semiconductor device of claim 10 ,
wherein the plurality of vertical structures comprises a vertical memory structure that is in contact with the intermediate pattern layer and is spaced apart from the intermediate structure,
wherein the vertical memory structure includes a core region, a channel layer on a side surface and a bottom surface of the core region, and a data storage structure on an outer surface and a bottom surface of the channel layer,
wherein the data storage structure comprises a first dielectric layer, a second dielectric layer, and a data storage layer between the first dielectric layer and the second dielectric layer, and
where

Assignees

• Samsung Electronics Co Ltd

Inventors

• Seo Yujin
• JUNG Euntaek
• Lee Byoungil
• Lee Seul
• Lee Joonhee
• Jung Changdae
• Choi Bonghyun
• Takaki Sejie

Classifications

• H10D30/69

  IGFETs having charge trapping gate insulators, e.g. MNOS transistors · CPC title

• H10D30/694

  characterised by the shapes, relative sizes or dispositions of the gate electrodes · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H10B43/27 Primary

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B41/10

  characterised by the top-view layout · CPC title