Semiconductor device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-10062707-B2
Application number	US-201715601474-A
Country	US
Kind code	B2
Filing date	May 22, 2017
Priority date	Nov 14, 2016
Publication date	Aug 28, 2018
Grant date	Aug 28, 2018

Abstract

Provided here may be a semiconductor device and a method of manufacturing the same. The semiconductor device may include a first source seed layer, a second source seed layer disposed over the first source seed layer at a position spaced apart from the first source seed layer with a source area interposed between the first source seed layer and the second source seed layer, cell plugs configured to penetrate through the second source seed layer and extend into the source area, the cell plugs being disposed at positions spaced apart from the first source seed layer. The semiconductor device may also include an interlayer source layer configured to fill the source area.

First claim

What is claimed is:

1. A semiconductor device comprising:
a first source seed layer;
a second source seed layer disposed over the first source seed layer at a position spaced apart from the first source seed layer with a source area interposed between the first source seed layer and the second source seed layer;
cell plugs configured to penetrate through the second source seed layer and extend into the source area, the cell plugs being disposed at positions spaced apart from the first source seed layer; and
an interlayer source layer configured to fill the source area,
wherein each of the cell plugs has a bottom coplanar with a surface of the interlayer source layer.

2. The semiconductor device according to claim 1 , further comprising
at least one dummy plug configured to penetrate through the second source seed layer and extend into the first source seed layer via the source area.

3. The semiconductor device according to claim 2 , further comprising
interlayer insulating layers and conductive patterns alternately stacked on the second source seed layer.

4. The semiconductor device according to claim 3 , wherein the cell plugs and the at least one dummy plug extend to penetrate through the interlayer insulating layers and the conductive patterns.

5. The semiconductor device according to claim 2 , wherein the at least one dummy plug extends toward the first source seed layer and penetrates through an upper portion of the first source seed layer, and the at least one dummy plug has a length greater than a length of each of the cell plugs.

6. The semiconductor device according to claim 2 , wherein each of the cell plugs comprises:
a first channel layer configured to penetrate through the second source seed layer and extend into the source area; and
a multilayer pattern configured to enclose an outer surface of a portion of the first channel layer that penetrates through the second source seed layer.

7. The semiconductor device according to claim 6 , wherein the at least one dummy plug comprises:
a second channel layer configured to penetrate through the second source seed layer and extend into the first source seed layer via the source area;
a first multilayer pattern configured to enclose an outer surface of a first part of the second channel layer that penetrates through the second source seed layer; and
a second multilayer pattern configured to enclose an outer surface of a second part of the second channel layer that penetrates through an upper portion of the first source seed layer.

8. The semiconductor device according to claim 7 , wherein the first multilayer pattern and the second multilayer pattern are separated from each other by the interlayer source layer.

9. The semiconductor device according to claim 7 , wherein the multilayer pattern and the first multilayer pattern are formed in the same layer.

10. The semiconductor device according to claim 7 , wherein the multilayer pattern and the first and second multilayer patterns are formed of the same material.

11. The semiconductor device according to claim 6 , wherein the multilayer pattern comprises:
a tunnel insulating layer configured to enclose the first channel layer;
a data storage layer configured to enclose the tunnel insulating layer; and
a blocking insulating layer configured to enclose the data storage layer.

Assignees

• Sk Hynix Inc

Inventors

• Lee Hyun Ho

Classifications

• H10P14/271

  characterised by the preparation of substrate for selective deposition · CPC title

• H01L27/249

  Electricity · mapped topic

• H01L29/1037

  Electricity · mapped topic

• H01L29/42348

  Electricity · mapped topic

• H01L21/02639

  Electricity · mapped topic