Three-dimensional memory device

US10510770B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10510770-B2
Application numberUS-201816127763-A
CountryUS
Kind codeB2
Filing dateSep 11, 2018
Priority dateMar 14, 2018
Publication dateDec 17, 2019
Grant dateDec 17, 2019

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  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A semiconductor device includes a base body portion, a stacked body, a pedestal portion, a plate portion, and first and second columnar portions. The base body portion includes a doped semiconductor film and a semiconductor portion. The doped semiconductor film includes first and second portions. The semiconductor portion includes a first region overlapping the first portion, and a second region overlapping the second portion and being a body different from the first region. The pedestal portion is provided in the second region. The plate portion contacts the pedestal portion and the first region. The first columnar portion includes a semiconductor layer. The semiconductor layer is adjacent to the plate portion with the stacked body interposed, and contacts the first region. The second columnar portion is adjacent to the plate portion with the stacked body interposed, and is adjacent to the pedestal portion with the second region interposed.

First claim

Opening claim text (preview).

What is claimed is: 1. A semiconductor device, comprising: a base body portion including a first layer and a second layer, the first layer being provided on a substrate with at least a first insulating film interposed, the first layer including a first portion and a second portion arranged along a first direction, the first portion being of a semiconductor, the second portion being of a semiconductor, the second layer including a first region and a second region, the first region being positioned on the first portion, the second region being positioned on the second portion, a portion of a source being formed of the first region; a stacked body provided above the base body portion, the stacked body alternately including a conductive layer and an insulating layer; a first pedestal portion provided inside at least the second layer, the first pedestal portion including a portion extending in the first direction in the second region of the second layer; a plate portion including at least a first insulator, being provided from an upper end of the stacked body to the second layer, extending in the first direction, and contacting the first region of the second layer and the portion of the first pedestal portion extending in the first direction; a plurality of first columnar portions, the plurality of first columnar portions each including a semiconductor layer and a memory film, being provided from the upper end of the stacked body to the second layer, and being adjacent to the plate portion in a second direction with the stacked body interposed, the second direction crossing the first direction, the semiconductor layer contacting the first region of the second layer, the memory film including a charge trapping portion between the semiconductor layer and the conductive layer; and a plurality of second columnar portions including at least a second insulator, being provided from the upper end of the stacked body to the second layer, being adjacent to the plate portion in the second direction with the stacked body interposed, and being adjacent to the first pedestal portion in the second direction with the second region of the second layer interposed. 2. The device according to claim 1 , wherein the first pedestal portion further includes a portion extending in the second direction between the first region and the second region of the second layer and being connected to the portion extending in the first direction.

Assignees

Inventors

Classifications

  • of organic photoresist masks · CPC title

  • by chemical means · CPC title

  • using masks for insulating materials · CPC title

  • the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz · CPC title

  • the material being a silicon oxide, e.g. SiO2 · CPC title

Patent family

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Frequently asked questions

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What does patent US10510770B2 cover?
A semiconductor device includes a base body portion, a stacked body, a pedestal portion, a plate portion, and first and second columnar portions. The base body portion includes a doped semiconductor film and a semiconductor portion. The doped semiconductor film includes first and second portions. The semiconductor portion includes a first region overlapping the first portion, and a second regio…
Who is the assignee on this patent?
Toshiba Memory Corp
What technology area does this patent fall under?
Primary CPC classification H10W20/20. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Dec 17 2019 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 12 related publications on this page (citations in our corpus or others sharing the same primary CPC).