Nonvolatile memory device and method of fabricating same

Patent metadata

Field	Value
Publication number	US-11856772-B2
Application number	US-202016930381-A
Country	US
Kind code	B2
Filing date	Jul 16, 2020
Priority date	Jan 28, 2020
Publication date	Dec 26, 2023
Grant date	Dec 26, 2023

Abstract

A nonvolatile memory device and method of fabricating same, the nonvolatile memory device including a substrate; a first semiconductor layer on the substrate; an etching stop film including a metal oxide on the first semiconductor layer; a mold structure including second semiconductor layers and insulating layers alternately stacked on the etching stop film; a channel hole penetrating through at least one of the mold structure, the etching stop film, the second semiconductor layer and the substrate; and a channel structure extending along a side wall of the channel hole, including an anti-oxidant film, a first blocking insulation film, a second blocking insulation film, a charge storage film, a tunnel insulating film and a channel semiconductor sequentially formed along the side wall of the channel hole. The first semiconductor layer contacts the first blocking insulation film, the second blocking insulation film, the charge storage film, and the tunnel insulating film.

First claim

What is claimed is:

1. A nonvolatile memory device comprising:
a substrate;
a first semiconductor layer on the substrate;
an etching stop film including a metal oxide on the first semiconductor layer;
a mold structure including second semiconductor layers and insulating layers alternately stacked on the etching stop film;
a channel hole which penetrates the mold structure, the etching stop film, the first semiconductor layer and the substrate in a first direction; and
a channel structure which extends inside the channel hole and along a side wall of the channel hole, wherein the channel structure includes an anti-oxidant film on the side wall of the channel hole, a first blocking insulation film on the anti-oxidant film, a second blocking insulation film on the first blocking insulation film, a charge storage film on the second blocking insulation film, a tunnel insulating film on the charge storage film and a channel semiconductor on the tunnel insulation film,
wherein the anti-oxidant film is in contact with the second semiconductor layers,
wherein the second semiconductor layers are polysilicon,
wherein the channel semiconductor does not contact the anti-oxidant film,
wherein the first semiconductor layer penetrates the anti-oxidant film in a second direction intersecting the first direction, and directly contacts the first blocking insulation film, the second blocking insulation film, the charge storage film, and the tunnel insulating film, and
wherein the anti-oxidant film is AlN.

2. The nonvolatile memory device of claim 1 , wherein the metal oxide is HfO 2 .

3. The nonvolatile memory device of claim 1 , wherein a thickness of the etching stop film is the same as a thickness of the second semiconductor layers.

4. The nonvolatile memory device of claim 1 , further comprising:
a common source line plate between the substrate and the first semiconductor layer,
wherein the channel hole penetrates the mold structure, the etching stop film, the first semiconductor layer, and the common source line plate.

5. The nonvolatile memory device of claim 1 , wherein the second semiconductor layers are P-doped polysilicon.

6. The nonvolatile memory device of claim 5 , wherein the first semiconductor layer is N-doped polysilicon.

7. A nonvolatile memory device comprising:
a substrate;
a first semiconductor layer on the substrate;
an etching stop film including a metal oxide on the first semiconductor layer;
a mold structure including second semiconductor layers and insulating layers alternately stacked on the etching stop film;
a common source line which penetrates the mold structure, the etching stop film and the first semiconductor layer in a first direction, and includes conductive materials;
an insulating spacer between the mold structure and the common source line, the insulating spacer does not contact the first semiconductor layer;
a channel hole which penetrates the mold structure, the etching stop film, the first semiconductor layer and the substrate in the first direction; and
a channel structure which extends along a side wall of the channel hole, and includes an anti-oxidant film, a first blocking insulation film, a second blocking insulation film, a charge storage film, a tunnel insulating film and a channel semiconductor sequentially disposed on the side wall of the channel hole,
wherein the anti-oxidant film is in contact with the second semiconductor layers, wherein the second semiconductor layers are polysilicon,
wherein the first semiconductor layer penetrates the anti-oxidant film in a second direction intersecting the first direction, and directly contacts the first blocking insulation film, the second blocking insulation film, the charge storage film, and the tunnel insulating film,
wherein the channel semiconductor does not contact the anti-oxidant film,
wherein the common source line is electrically connected to the channel semiconductor through the substrate and the first semiconductor layer, and
wherein the anti-oxidant film is AlN.

8. The nonvolatile memory device of claim 7 , wherein the metal oxide is HfO 2 .

9. The nonvolatile memory device of claim 7 , wherein a thickness of the etching stop film is the same as a thickness of the second semiconductor layers.

10. The nonvolatile memory device of claim 7 , further comprising:
a common source line plate between the substrate and the first semiconductor layer,
wherein the channel hole penetrates through the mold structure, the etching stop film, the first semiconductor layer, and the common source line plate.

11. The nonvolatile memory device of claim 7 , further comprising:
an insulating spacer between the mold structure and the common source line, between the etching stop film and the common source line, and between the first semiconductor layer and the common source line.

12. The nonvolatile memory device of claim 11 , wherein the insulating spacer includes at least one insulating material.

13. The nonvolatile memory device of claim 11 , wherein the insulating spacer includes protrusions which respectively penetrate into the second semiconductor layers between the insulating layers and contact the common source line.

14. The nonvolatile memory device of claim 7 , wherein the second semiconductor layers are P-doped polysilicon.

15. The nonvolatile memory device of claim 14 , wherein the first semiconductor layer is N-doped polysilicon.

16. A nonvolatile memory device comprising:
a substrate; a first semiconductor layer on the substrate;
an etching stop film including a metal oxide on the first semiconductor layer;
a mold structure including second semiconductor layers and insulating layers alternately stacked on the etching stop film;
a common source line which penetrates the mold structure, the etching stop film and the first semiconductor layer in a first direction, and includes conductive materials;
a channel hole which penetrates the mold structure, the etching stop film, the first semiconductor layer and the substrate;
a channel structure which extends along a side wall of the channel hole, includes an anti-oxidant film, a first blocking insulation film, a second blocking insulation film, a charge storage film, a tunnel insulating film, a channel semiconductor and a filling pattern sequentially disposed on the side wall of the channel hole, and includes a channel pad on the channel semiconductor and the filling pattern;
an insulating spacer formed between the mold structure and the common source line, between the etching stop film and the common source line, and between the first semiconductor layer and the common source line;
a bit line contact electrically connected to the channel pad;
an interlayer insulating film which surrounds the bit line contact; and
a bit line disposed on the interlayer insulating film and electrically connected to the bit line contact,
wherein the insulating spacer does not contact the first semiconductor layer,
wherein the anti-oxidant film is in contact with the second semiconductor layers,
wherein the second semiconductor layers are polysilicon,
wherein the first semiconductor layer penetrates the anti-oxidant film in a second direction intersecting the first direction, and directly contacts the first blocking insulation film, the second blocking insulation film, the charge storage film, and the tunnel insulating film,
wherein the channel semiconductor does not contact the anti-oxidant film, and
wherein the first semiconductor layer penetrates the first blocking insulation film, the second blocking insulation film, the charge storage

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Seung Won
• Kim Tae Hun
• Park Min Cheol
• Shin Hye Ri
• Lim Jun Hee
• Cho Si Yeon

Classifications

• H10D30/69

  IGFETs having charge trapping gate insulators, e.g. MNOS transistors · CPC title

• H10D30/0413

  of FETs having charge-trapping gate insulators, e.g. MNOS transistors · CPC title

• H10D64/037 Primary

  comprising charge-trapping insulators · CPC title

• H10B43/27 Primary

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• G11C7/18

  Bit line organisation; Bit line lay-out · CPC title