Memory and method for forming memory

Patent metadata

Field	Value
Publication number	US-11856749-B2
Application number	US-202117455518-A
Country	US
Kind code	B2
Filing date	Nov 18, 2021
Priority date	May 22, 2020
Publication date	Dec 26, 2023
Grant date	Dec 26, 2023

Abstract

Embodiments of the present application provide a memory and a method for forming the memory. The method includes: providing a substrate, and forming a bit line structure on the substrate and a first protective layer; forming a dielectric layer with which a gap between the adjacent bit line structures is filled; forming a second protective layer to cover a top surface of the first protective layer and a top surface of the dielectric layer; removing part of the dielectric layer and part of the second protective layer to form a capacitor contact hole, and exposing the first protective layer between two adjacent ones of the capacitor contact holes; forming a conductive layer with which the capacitor contact hole is filled and the top surface of the exposed first protective layer is covered, and etching part of the conductive layer to form a separate capacitor contact structure.

First claim

What is claimed is:

1. A method for forming a memory, comprising:
providing a substrate, and forming a bit line structure on the substrate and a first protective layer on a top surface of the bit line structure;
forming a dielectric layer with which a gap between two adjacent ones of the bit line structures is filled, wherein a top surface of the dielectric layer is flush with a top surface of the first protective layer;
forming a second protective layer to cover the top surface of the first protective layer and the top surface of the dielectric layer;
removing part of the dielectric layer and part of the second protective layer in a direction perpendicular to an extension direction of the bit line structure to form a capacitor contact hole, and exposing the first protective layer between two adjacent ones of the capacitor contact holes in the direction which is perpendicular to the extension direction of the bit line structure, wherein an unremoved part of the dielectric layer forms an isolating structure, and a material of the second protective layer is different from a material of the isolating structure;
forming a conductive layer to fill the capacitor contact holes and cover the top surface of the first protective layer exposed, wherein a top surface of the conductive layer is flush with a top surface of the second protective layer; and
etching part of the conductive layer to form a separate capacitor contact structure wherein an unetched part of the conductive layer forms bugles extending at intervals in a preset direction and on the top surface of part of the first protective layer, and the preset direction and the extension direction of the bit line structure form an angle.

2. The method for forming the memory according to claim 1 , wherein etching the part of the conductive layer to form the separate capacitor contact structure comprises:
forming a contact mask layer on the top surfaces of both the conductive layer and the second protective layer;
exposing, by the contact mask layer, both the conductive layer and the second protective layer of a preset width in the preset direction, wherein the contact mask layer and the conductive layer and the second protective layer exposed are alternately arranged perpendicular to the preset direction, and the angle is greater than 0° and not equal to 90°;
etching the conductive layer exposed until part of the top surface of the first protective layer is exposed; and
removing the contact mask layer, wherein the rest of the conductive layer serves as the capacitor contact structure.

3. The method for forming the memory according to claim 1 , wherein forming the bit line structure on the substrate and the first protective layer on the top surface of the bit line structure comprises:
forming a bit line multi-layer on the substrate and a first protective film at a top of the bit line multi-layer;
forming a patterned bit line mask layer on a top surface of the first protective film, and etching the first protective film and the bit line multi-layer by taking the patterned bit line mask layer as a mask to form the bit line structure and the first protective layer on the top surface of the bit line structure; and
removing the patterned bit line mask layer.

4. The method for forming the memory according to claim 3 , wherein forming the bit line multi-layer on the substrate comprises:
forming a separate bit line contact layer on the substrate, wherein the bit line contact layer is connected to an active area in the substrate;
forming a bottom dielectric layer on the substrate to fill a gap between two adjacent ones of the bit line contact layers, wherein a top surface of the bottom dielectric layer is flush with a top surface of the bit line contact layer;
forming a metal layer on the top surfaces of both the bottom dielectric layer and the bit line contact layer; and
forming a top dielectric layer on a top surface of the metal layer.

5. The method for forming the memory according to claim 1 , wherein removing the part of the dielectric layer and the part of the second protective layer in the direction perpendicular to the extension direction of the bit line structure to form the capacitor contact hole comprises:
forming a dielectric mask layer on the top surface of the second protective layer;
etching the part of the second protective layer in the direction perpendicular to the extension direction of the bit line structure by taking the dielectric mask layer as a mask until the top surfaces of the part of the first protective layer and the part of the dielectric layer are exposed; and
removing the exposed part of the dielectric layer to form the capacitor contact hole.

6. The method for forming the memory according to claim 1 , wherein after forming the capacitor contact hole and before forming the conductive layer with which the capacitor contact hole is filled, the method further comprises:
forming an isolating film on the substrate, wherein the isolating film covers the second protective layer and the exposed first protective layer and both a side wall and a bottom of the capacitor contact hole; and
removing the isolating film on the top surface of the second protective layer, on the top surface of the exposed first protective layer and at the bottom of the capacitor contact hole, to form an isolating layer on the side wall of the capacitor contact hole.

7. The method for forming the memory according to claim 1 , wherein the conductive layer comprises a first conductive layer and a second conductive layer that are made from different materials; a top surface of the second conductive layer is flush with the top surface of the second protective layer; and the second conductive layer further covers the top surface of the first protective layer in the direction perpendicular to the extension direction of the bit line structure.

8. The method for forming the memory according to claim 7 , wherein forming the conductive layer with which the capacitor contact hole is filled comprises:
forming the first conductive layer in the capacitor contact hole, wherein a top surface of the first conductive layer is lower than the top surface of the first protective layer;
forming a top conductive film on the top surface of the first conductive layer, the top surface of the first protective layer and the top surface of the second protective layer; and
etching the top conductive film to form the second conductive layer.

9. The method for forming the memory according to claim 1 , wherein after forming the separate capacitor contact structure, the method comprises:
forming an isolating mask layer on the top surface of the second protective layer;
patterning the second protective layer at a top of the capacitor contact structure in the extension direction of the bit line structure by taking the isolating mask layer as a mask to expose the dielectric layer between two adjacent ones of the capacitor contact structures;
removing the dielectric layer between the two adjacent ones of the capacitor contact structures to form an air gap; and
forming a sealing layer to seal a top of the air gap.

10. The method for forming the memory according to claim 1 , wherein forming the dielectric layer to fill the gap between the two adjacent ones of the bit line structures comprises:
forming a dielectric film to fill the gap between the two adjacent ones of the bit line structures, wherein the dielectric film covers the bit line structure; and
removing the dielectric film that is higher than the top surface of the bit line structure, wherein the dielectric film that remains forms the dielectric layer.

11. A memory, comprising:
a substrate and a bit line struct

Assignees

• Changxin Memory Tech Inc

Inventors

• Li Ran

Classifications

• H10B12/0335 Primary

  Making a connection between the transistor and the capacitor, e.g. plug · CPC title

• H10B12/315 Primary

  with the capacitor higher than a bit line · CPC title

• H10B12/482

  Bit lines · CPC title

• H10B12/01 Primary

  Manufacture or treatment · CPC title

• H10B12/00

  Dynamic random access memory [DRAM] devices · CPC title