Printed circuit board

Patent metadata

Field	Value
Publication number	US-11856701-B2
Application number	US-202217673405-A
Country	US
Kind code	B2
Filing date	Feb 16, 2022
Priority date	Nov 17, 2021
Publication date	Dec 26, 2023
Grant date	Dec 26, 2023

Abstract

A printed circuit board includes: a first insulating layer including a first cavity and a second cavity; a first electronic component disposed in the first cavity and including a first pad disposed in a first surface direction of the first insulating layer; a second electronic component disposed in the second cavity and including a second pad disposed in a second surface direction, facing the first surface direction, of the first insulating layer; a second insulating layer disposed on each of first and second surfaces of the first insulating layer and in the first cavity to cover the first electronic component; and a third insulating layer disposed on the first surface of the first insulating layer and in the second cavity to cover the second electronic component.

First claim

What is claimed is:

1. A printed circuit board comprising:
a first insulating layer including a first cavity and a second cavity;
a first electronic component disposed in the first cavity and including a first pad disposed in a first direction;
a second electronic component disposed in the second cavity and including a second pad disposed in a second direction opposite to the first direction;
a second insulating layer disposed in the first cavity and covering the first electronic component; and
a third insulating layer disposed in the second cavity and covering the second electronic component,
wherein an upper surface of the second pad is substantially coplanar with an upper surface of the second insulating layer.

2. The printed circuit board of claim 1 , wherein the second and third insulating layers include the same composition.

3. The printed circuit board of claim 1 , wherein the second insulating layer is disposed on each of first and second surfaces opposing each other of the first insulating layer, and
the third insulating layer is disposed on the first surface of the first insulating layer.

4. The printed circuit board of claim 1 , wherein the third insulating layer is in contact with a first surface of the second insulating layer.

5. The printed circuit board of claim 1 , wherein at least a portion of the third insulating layer is in contact with the first pad of the first electronic component.

6. The printed circuit board of claim 1 , further comprising a fourth insulating layer disposed on a second surface of the second insulating layer opposing a first surface of the second insulating layer.

7. The printed circuit board of claim 6 , wherein at least a portion of the fourth insulating layer is in contact with the second pad of the second electronic component.

8. The printed circuit board of claim 6 , further comprising:
a first wiring layer disposed on the third insulating layer;
a first via disposed in the third insulating layer and connecting the first wiring layer to the first pad of the first electronic component;
a second wiring layer disposed on the fourth insulating layer; and
a second via disposed in the fourth insulating layer and connecting the second wiring layer to the second pad of the second electronic component.

9. The printed circuit board of claim 1 , further comprising a fifth insulating layer disposed on a first surface of the second insulating layer and being in contact with the third insulating layer.

10. The printed circuit board of claim 9 , wherein the second, third, and fifth insulating layers include the same composition.

11. The printed circuit board of claim 1 , wherein the second insulating layer includes first and second surfaces opposing each other, and
the first pad of the first electronic component and the first surface of the second insulating layer are coplanar with each other.

12. The printed circuit board of claim 1 , wherein the second insulating layer includes first and second surfaces opposing each other, and
the second pad of the second electronic component and the second surface of the second insulating layer are coplanar with each other.

13. The printed circuit board of claim 1 , wherein the second insulating layer includes first and second surfaces opposing each other,
the first pad of the first electronic component and the first surface of the second insulating layer are coplanar with each other, and
the second pad of the second electronic component and the second surface of the second insulating layer are coplanar with each other.

14. A printed circuit board comprising:
a first insulating layer having first and second surfaces opposing each other, and including a first cavity penetrating through the first and second surfaces;
a first electronic component disposed in the first cavity and including a first pad;
a second insulating layer disposed in the first cavity to cover the first electronic component, and extending on the first and second surfaces of the first insulating layer;
a second electronic component including a second pad and disposed in a second cavity which penetrates through the first insulating layer and the second insulating layer;
a third insulating layer disposed in the second cavity to cover the second electronic component, and extending on the second insulating layer; and
a fifth insulating layer disposed between the second insulating layer and the third insulating layer,
wherein the first pad and the second pad are disposed in opposite directions.

15. The printed circuit board of claim 14 , further comprising a fourth insulating layer disposed on the second insulating layer and being in contact with the second pad.

16. The printed circuit board of claim 15 , wherein the third insulating layer is in contact with the second insulating layer and the first pad.

17. The printed circuit board of claim 14 , wherein the second cavity also penetrates through the fifth insulating layer, and
the fifth insulating layer is in contact with the second insulating layer and the first pad.

Assignees

• Samsung Electro Mech

Inventors

• Kwon Hyun Woo
• Park Ki Ran
• Jung Kyeong Yub
• Lee Jin Uk
• Lee Jae Heun

Classifications

• H05K1/185 Primary

  associated with components encapsulated in the insulating substrate of the PCBs; associated with components incorporated in internal layers of multilayer circuit boards · CPC title

• H05K1/112

  directly combined with via connections · CPC title

• H05K1/183

  associated with components mounted in and supported by recessed areas of the PCBs · CPC title

• H05K3/4697 Primary

  having cavities, e.g. for mounting components (H05K3/4691 takes precedence) · CPC title

• H05K1/0216

  Reduction of cross-talk, noise or electromagnetic interference (grounding H05K1/0215) · CPC title