Adaptive spur cancellation techniques and multi-phase injection locked tdc for digital phase locked loop circuit
US-2016359493-A1 · Dec 8, 2016 · US
US11855649B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-11855649-B2 |
| Application number | US-202117399981-A |
| Country | US |
| Kind code | B2 |
| Filing date | Aug 11, 2021 |
| Priority date | Jun 26, 2018 |
| Publication date | Dec 26, 2023 |
| Grant date | Dec 26, 2023 |
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A spur measurement system uses a first device with a spur cancellation circuit that cancel spurs responsive to a frequency control word identifying a spurious tone of interest. A device under test generates a clock signal and supplies the clock signal to the first device through an optional divider. The spur cancellation circuit in the first device generates sine and cosine weights at the spurious tone of interest as part of the spur cancellation process. A first magnitude of the spurious tone in a phase-locked loop in the first device is determined according to the sine and cosine weights and a second magnitude of the spurious tone in the clock signal is determined by the first magnitude divided by gains associated with the first device.
Opening claim text (preview).
What is claimed is: 1. A method of determining a presence of a spurious tone in a signal, the method comprising: receiving an indication of a first frequency corresponding to a spurious tone to be measured in a first signal; generating a second signal in a phase-locked loop based on the first signal and a feedback signal; determining a presence of the spurious tone in the second signal based on scale factors of a spur cancellation signal; determining a first magnitude of the spurious tone in the second signal based on the scale factors of the spur cancellation signal; and dividing the first magnitude of the spurious tone in the second signal, which was determined based on the scale factors of the spur cancellation signal, by a plurality of gain factors to determine a second magnitude of the spurious tone in the first signal. 2. The method of claim 1 wherein the plurality of gain factors include a first gain of a phase detector. 3. The method of claim 2 wherein the plurality of gain factors further include a second gain associated with a time-to-digital converter. 4. The method of claim 1 wherein the indication of the first frequency includes a frequency control word. 5. The method of claim 1 further comprising: generating the second signal in a time-to-digital converter in the phase-locked loop; and controlling an oscillator of the phase-locked loop using the second signal. 6. The method of claim 1 wherein the first signal is generated by dividing an output signal from a device under test. 7. The method of claim 1 further comprising detecting presence of a spurious tone corresponding to a second frequency in the first signal. 8. The method of claim 1 further comprising receiving a second indication of a second frequency corresponding to an additional spurious tone to be measured in the first signal. 9. A spur measurement system comprising: a phase-locked loop responsive to an indication of a spurious tone in a first signal, the phase-locked loop configured to determine the presence of the spurious tone in a second signal generated based on the first signal, to determine a first magnitude of the spurious tone in the second signal based on scale factors of a spur cancellation signal, and to determine a second magnitude of the spurious tone in the first signal by dividing the first magnitude, which was determined based on the scale factors of the spur cancellation signal, by a plurality of gain factors of the phase-locked loop. 10. The system of claim 9 wherein the plurality of gain factors include a first gain of a phase detector. 11. The system of claim 10 wherein the plurality of gain factors further include a second gain associated with a time-to-digital converter. 12. The system of claim 9 wherein the phase-locked loop further includes an oscillator and a time-to-digital converter, the time-to-digital converter configured to generate the second signal, the phase-locked loop configured to control the oscillator using the second signal. 13. The system of claim 9 wherein the indication of the spurious tone includes a frequency control word. 14. The system of claim 9 further comprising a divider circuit configured to generate the first signal by dividing a signal from a device under test. 15. The system of claim 9 wherein the phase-locked loop is further configured to determine presence of an additional spurious tone in the first signal.
using special filtering or amplification characteristics in the loop (H03L7/087 - H03L7/091 take precedence) · CPC title
Measuring noise figure; Measuring signal-to-noise ratio · CPC title
Clock circuits aspects, e.g. test clock circuit details, timing aspects for signal generation, circuits for testing clocks (G01R31/31725 takes precedence; concerning scan test G01R31/318552, for tester hardware G01R31/31922) · CPC title
Time-to-digital converters [TDC] (analog-to-digital converters with intermediate conversion to time or phase H03M1/50, H03M1/60) · CPC title
using more than one loop · CPC title
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